Wafer to wafer direct bonding using surfaces activated by hydrogen plasma treatment

Choi, Woo Beom; Ju, Chul-Won; Ju, Byong-Sun; Sung, Man Young

doi:10.1109/iemt.1999.804810

Cited by 1 publication

(2 citation statements)

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“…This process does not damage the surface of sensitive substrates, and when configured in the indirect mode can additionally be applied to electronic devices. studied and modeled by a number of authors, characterizing the influence of various parameters on the strength and quality of the resultant bond [24][25][26][27][28][29][30][31][32]. Alternatively, surfaces have been activated by ion bombardment or wet chemical means [20].…”

Section: Plasma Activationmentioning

confidence: 99%

“…It has previously been reported that strong hydrophilic bonding between silicon dioxide and silicon can be achieved at low annealing temperatures (< 400 • C) by exposing the wafers to the low-pressure plasma of various gases O 2 , Ar, N 2 , and others, prior to bonding [20][21][22][23]. This process has been studied and modeled by a number of authors, characterizing the influence of various parameters on the strength and quality of the resultant bond [24][25][26][27][28][29][30][31][32]. Alternatively, surfaces have been activated by ion bombardment or wet chemical means [20].…”

Section: Plasma Activationmentioning

confidence: 99%

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A new low-temperature high-aspect-ratio MEMS process using plasma activated wafer bonding

Galchev

Welch

Najafi³

2011

J. Micromech. Microeng.

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This paper presents the development and characterization of a new high-aspect-ratio MEMS process. The silicon-on-silicon (SOS) process utilizes dielectric barrier discharge surface activated low-temperature wafer bonding and deep reactive ion etching to achieve a high aspect ratio (feature width reduction-to-depth ratio of 1:31), while allowing for the fabrication of devices with a very high anchor-to-anchor thermal impedance (>0.19 × 10 6 K W −1). The SOS process technology is based on bonding two silicon wafers with an intermediate silicon dioxide layer at 400 • C. This SOS process requires three masks and provided numerous advantages in fabricating several MEMS devices, as compared with silicon-on-glass (SOG) and silicon-on-insulator (SOI) technology, including better dimensional and etch profile control of narrow and slender MEMS structures. Additionally, by patterning the intermediate SiO 2 insulation layer before bonding, footing is reduced without any extra processing, as compared to both SOG and SOI. All SOS process steps are CMOS compatible.

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