Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

Abstract

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Lab-on-a-chip devices: How to close and plug the lab?

“…epoxy or parylene) and typically PDMS-based microfluidic structures (straight channels or reservoirs) are then interfaced to the surface of a CMOS chip. There has been also some recent activity to embed CMOS chips into larger substrates and to route the CMOS I/O pads to the periphery of the carrier using a metal patterning step [235,236]. Although thousands of CMOS chips can be manufactured at a low-cost using wafer-level batch processing, these post-processing and integration/packaging steps can reduce the yield and rise the overall cost considerably.…”

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces

“…There can be a substantial gap between the edge of the IC and the handle wafer, which inhibits conformal application of photoresist and results in discontinuity of the metal traces used for I/O connections. An elegant solution is to create a custom hole for the IC using the chip itself to define the lateral dimensions of the cavity (self-aligned masking) [59]. Other approaches to the gap issue have been to create holes that are larger than the chip and use material such as spin-on-glass (SOG) or polymers to bridge the gap and bring the chip flush and level with the surface [16].…”

“…Hybrid systems have also been demonstrated in which the microfluidic channels were patterned in a material such as acrylic or glass and the fluid manifold sealed to the surface of the IC using an intermediate gasket material such as PDMS [59]. Alternatively, microchannels can be fabricated within the encapsulation material itself by using a soluble patternable material around which the encapsulation material is allowed to cure [74].…”

Hybrid Silicon Photonic Integrated Circuit Technology

“…Further integration can be achieved with the method presented in [95] and [96] and schematically shown in Fig. 35(a) and (b).…”