Wafer-level chip size package (WL-CSP)

Topper, Michael J.; Fehlberg, S.; Scherpinski, K.; Karduck, C.; Glaw, V.; Heinricht, K.; Coskina, P.; Ehrmann, O.; Reichl, H.

doi:10.1109/6040.846640

Cited by 27 publications

(2 citation statements)

References 3 publications

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“…For example, Fraunhofer IZM/TU Berlin [2,3] and IME Singapore [4,14], proposed the double-bump WLPs to increase solder joint standoff height. Fujitsu Ltd. [5] presented a shorter Cu post design to enhance solder joint reliability.…”

Section: Introductionmentioning

confidence: 99%

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Zhang

Kripesh

Chai

et al. 2008

Microelectronics Reliability

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Section: Introductionmentioning

confidence: 99%

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Zhang

Kripesh

Chai

et al. 2008

Microelectronics Reliability

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“…Wafer-Level-Packaging has been established as an optimal packaging solution for microelectronic devices [1]. Further miniaturization in 2-D is not possible due to true chip size packaging.…”

Section: Introductionmentioning

confidence: 99%

3-D thin chip integration technology - from technology development to application

Fritzsch

Mrossko

Baumgärtner

et al. 2009

2009 IEEE International Conference on 3D System Integration

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3-D technologies open a wide range of chip integration possibilities for microelectronic systems.Most of these technologies are using Through-Silicon Vias (TSV). One disadvantage of this technology is the high investment for new equipment and processing cost for Si etching and metallization. The thin chip integration technology (TCI) presented in this paper is based upon existing WLP infrastrcuture: The core component of this planar integration technology is the embedding of ultra-thin chips into a multi layer thin film routing on a larger sized substrate chip on wafer level. All process steps are performed with standard back end equipment used for redistribution and other wafer level packaging technologies. Using advanced grinding and etching technologies thinning of CMOS chips is possible down to a thickness of 20 to 40 microns with high yield. These ultra-thin chips can be integrated into BCB-copper multi layer redistribution on wafer level.A test chip with peripheral arranged daisy chains was thinned down to a thickness of 35µm. This thin chip was mounted onto a larger substrate chip on wafer level which also contains daisy chain interconnection between the embedded chip and the substrate. A third smaller daisy chain chip was flip chip mounted onto the two chips to result in a three level chip interconnection stack. The technology development was accompanied by electrical characterizations and reliability investigations including temperature cycle test between -55°C and 125°C. Beside this technological investigation a thermo-mechanical model was developed to investigate the stress accumulation during individual process steps as well as thermal cycling steps. The simulation indicates possible regions with a higher material failure risk during life time in accordance with the experimental evaluation and potential for further optimization.In addition to the technology development first examples of application will be given. Using the thin chip integration technology a functional demonstrator for wireless activity monitoring was realized within the e-CUBES project founded by the European Commision. A second functional TCI demonstrator will be realized within the RESTLES project, founded by the German government. This demonstrator is focused on the conditions in the automotive industry.978-1-4244-4512-7/09/$25.00 ©2009 IEEE

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Introduction into Photonic Packaging

Fischer-Hirchert

2015

Photonic Packaging Sourcebook

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Wafer-level chip size package (WL-CSP)

Cited by 27 publications

References 3 publications

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

3-D thin chip integration technology - from technology development to application

Introduction into Photonic Packaging

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