3-D thin chip integration technology - from technology development to application

Abstract

3-D technologies open a wide range of chip integration possibilities for microelectronic systems.Most of these technologies are using Through-Silicon Vias (TSV). One disadvantage of this technology is the high investment for new equipment and processing cost for Si etching and metallization. The thin chip integration technology (TCI) presented in this paper is based upon existing WLP infrastrcuture: The core component of this planar integration technology is the embedding of ultra-thin chips into a multi layer thin film routing on a larger sized substrate chip on wafer level. All process steps are performed with standard back end equipment used for redistribution and other wafer level packaging technologies. Using advanced grinding and etching technologies thinning of CMOS chips is possible down to a thickness of 20 to 40 microns with high yield. These ultra-thin chips can be integrated into BCB-copper multi layer redistribution on wafer level.A test chip with peripheral arranged daisy chains was thinned down to a thickness of 35µm. This thin chip was mounted onto a larger substrate chip on wafer level which also contains daisy chain interconnection between the embedded chip and the substrate. A third smaller daisy chain chip was flip chip mounted onto the two chips to result in a three level chip interconnection stack. The technology development was accompanied by electrical characterizations and reliability investigations including temperature cycle test between -55°C and 125°C. Beside this technological investigation a thermo-mechanical model was developed to investigate the stress accumulation during individual process steps as well as thermal cycling steps. The simulation indicates possible regions with a higher material failure risk during life time in accordance with the experimental evaluation and potential for further optimization.In addition to the technology development first examples of application will be given. Using the thin chip integration technology a functional demonstrator for wireless activity monitoring was realized within the e-CUBES project founded by the European Commision. A second functional TCI demonstrator will be realized within the RESTLES project, founded by the German government. This demonstrator is focused on the conditions in the automotive industry.978-1-4244-4512-7/09/$25.00 ©2009 IEEE

3D integration review

“…Many publications over the last several years have indicated that companies are either already manufacturing 3D chips or have plans to do so in the near future [65][66][67][68][69][70][71][72][73][74][75][76][77][78]. Ultimately, the success of any manufacturable 3D integration solution rides on several factors: 1) the choice of TSV technology, which in turn is determined by its compatibility with the rest of the fabrication process, including the bonding stage and method, and the requirements that are placed upon it from a systems perspective; 2) the robustness and thermo-mechanical reliability of the fully integrated structure; and 3) cost/yield considerations.…”

(Invited) 3D Integration in Silicon Technology

“…Modeling shows therefore that 3Di can deliver benefits that are not possible in the 2D regime. Recent publications (3)(4)(5)(6)(7)(8) are an indication that semiconductor manufacturers agree, and have already started 3D chip production or have plans to do so in the near future. However, 3D fabrication involves critical choices in bonding level and method, and TSV process and integration.…”