W-band frequency synthesis using a Ka-band PLL and two different frequency triplers

Chen, Zhiming; Wang, Chuncheng; Heydari, Payam

doi:10.1109/rfic.2011.5940607

Cited by 18 publications

(7 citation statements)

References 4 publications

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“…This method readily lowers the operation frequency of the LO distribution network and reduces the power consumption compared to a 90 GHz LO generation/distribution network [25]. As for the frequency tripler design, the injectionlocking topology is preferred over a harmonic-based structure since it can achieve higher power efficiency [26]. Furthermore, this method offers better phase noise than directly designing a 96 GHz PLL.…”

Section: A Architecturementioning

confidence: 99%

“…Injection-locking operation is realized by feeding the 3rd harmonic of the input signal generated by & into the emitters of ILO. Transistors & reuse part of the DC current of the tank and are biased in Class-AB regime for maximum 3rd harmonic generation [26]. The 96 GHz output signals are taken out from the collectors of & through a cascode buffer stage to minimize leakage of the 32 GHz injection signal at the output.…”

Section: Ilftmentioning

confidence: 99%

“…The test chip for Ka-band PLL and ILFT has been fabricated in the same technology to characterize the performance of LO generation circuit (see [26]). The single-ended 96 GHz output spectrum measured at the output of the ILFT is shown in Fig.…”

Section: ) Lomentioning

confidence: 99%

See 2 more Smart Citations

A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna

Chen

Wang

Yao

et al. 2012

IEEE J. Solid-State Circuits

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This paper presents a W-band 2 2 focal-plane array (FPA) for passive millimeter-wave imaging in a standard 0.18 m SiGe BiCMOS process ( GHz). The FPA incorporates four Dicke-type receivers representing four imaging pixels. Each receiver employs the direct-conversion architecture consisting of an on-chip slot folded dipole antenna, an SPDT switch, a low noise amplifier, a single-balanced mixer, an injection-locked frequency tripler (ILFT), an IF variable gain amplifier, a power detector, an active bandpass filter and a synchronous demodulator. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four local ILFTs. The measured LO phase noise is at 1 MHz offset from the 96 GHz carrier. This imaging receiver (without antenna) achieves a measured average responsivity and noise equivalent power of 285 MV/W and 8.1 , respectively, across the 86-106 GHz bandwidth, which results a calculated NETD of 0.48 K with a 30 ms integration time. The system NETD increases to 3 K with on-chip antenna due to its low efficiency at W-band. MMW images have been generated in transmission mode. This work demonstrates the highest integration level of any silicon-based systems in the 94 GHz imaging band.

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Section: A Architecturementioning

confidence: 99%

Section: Ilftmentioning

confidence: 99%

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A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna

Chen

Wang

Yao

et al. 2012

IEEE J. Solid-State Circuits

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“…However, having a power-efficient tunable signal source is necessary for many practical applications. A conventional and widely used way of controlling the oscillation frequency is to implement varactors in an LC oscillator [12], [13]. Nevertheless, a tight tradeoff exists between quality factor ( -factor) and tuning ratio of varactors, which will be more stringent at higher frequencies.…”

Section: Introductionmentioning

confidence: 99%

A 200-GHz Inductively Tuned VCO With $-$7-dBm Output Power in 130-nm SiGe BiCMOS

Chiang

Momeni

Heydari

2013

IEEE Trans. Microwave Theory Techn.

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“…The PLDRO is the most widely used for a local oscillator for such high frequency bands due to its superior phase noise characteristics compared with the PLL IC based approach. Millimeter wave SiGe based integer-N PLL IC phase noise performance has recently improved substantially [1][2][3], but fractional PLL with the same technology still shows inadequate performance compared with its integer counterpart, i.e., about 90 dB in-band phase noise and less than 70 dB spurious [4,5]. This paper presents a PLDRO structure that has output frequency that is not an integer multiple of the reference frequency, and verifies the structure by analyses and experiments.…”

Section: Introductionmentioning

confidence: 88%

Implementation of a Pldro With a Fractional Multiple Frequency of Reference

Chang¹,

Park²

2014

PIER Letters

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Abstract-A PLDRO (Phase Locked Dielectric Resonator Oscillator) with the output frequency of a fractional multiple of reference is proposed and implemented. The key element in the proposed PLDRO is an image rejection mixer placed between a VCDRO (Voltage Controlled Dielectric Resonator Oscillator) and SPD (Sampling Phase Detector). The image rejection mixer shifts the coupled signal from the VCDRO before the signal feeds the SPD. Therefore, the output frequency of the PLDRO can be realized such that it is not harmonically related with its reference frequency. The frequency divider and multiplier generate the IF frequency for the mixer from the reference frequency. The general PLL (Phase Locked Loop) design parameters such as the damping coefficient and the natural frequency are derived for the proposed topology of the PLDRO. A 7.25 GHz PLDRO with a 100 MHz reference, intended for use as a local oscillator for a ka band Block-up Converter (BUC), is designed and measured. A BJT (Bipolar Junction Transistor) is used as an active component of the VCDRO and a modified two micro-strip line coupled DR model is presented and used for frequency tuning range estimation. The measured phase noise at 10 kHz/100 kHz offset is 101 dBc/Hz and 115 dBc/Hz, respectively. The fabricated PLDRO size is 100 mm by 105 mm by 23 mm including a 100 MHz reference crystal oscillator.

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W-band frequency synthesis using a Ka-band PLL and two different frequency triplers

Cited by 18 publications

References 4 publications

A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna

A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna

A 200-GHz Inductively Tuned VCO With $-$7-dBm Output Power in 130-nm SiGe BiCMOS

Implementation of a Pldro With a Fractional Multiple Frequency of Reference

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