Voltage-mode ultra-low power four quadrant multiplier using subthreshold PMOS

Abstract

A voltage-mode ultra low power four quadrant analog multiplier using subthreshold PMOS is presented in this paper. PMOS substract cell and combiner cell operating in the subthreshold region are used to lower the voltage-mode multiplier power consumption. Simulation results of the multiplier demonstrate a linearity error of 0.8%, a maximum THD of 4%, a −3 dB bandwidth of 1.4 MHz, and a power consumption of 77 nW with 100 fF load capacitor at a supply voltage of 0.6 V using a TSMC 0.18 um CMOS process.

Four-quadrant multiplier using the floating-bulk technique for rail-to-rail input range and insensitivity to different input dc levels

“…The Gilbert cell, shown in Fig. 1 [1], is the base for many variations of this type of multipliers [2]- [10]. It consists of two cross-coupled differential pairs formed by transistors M1-M4 and controlled by one differential input signal 𝑉 𝑥𝑦 = 𝑉 𝑥 − 𝑉 𝑦 .…”

A 31.5-to-40.5 GHz injection-locked CMOS frequency tripler with injection-current enhancement technique

“…In general, the frequency multiplier can be realized with the harmonic amplifier [6,7,8] and injection locked frequency multiplier (ILFM) structures [9,10,11,12,13]. With the harmonic amplifier structure, the frequency multiplier can achieves relatively large bandwidth, but it consumes a high power consumption due to the low harmonic power efficiency.…”