VLSI design of low‐cost and high‐precision fixed‐point reconfigurable FFT processors

Abstract

Fast Fourier transform (FFT) plays an important role in digital signal processing systems. In this study, the authors explore the very large-scale integration (VLSI) design of high-precision fixed-point reconfigurable FFT processor. To achieve high accuracy under the limited wordlength, this study analyses the quantisation noise in FFT computation and proposes the mixed use of multiple scaling approaches to compensate the noise. In addition, a statistics-based optimisation scheme is proposed to configure the scaling operations of the cascaded arithmetic blocks at each stage for yielding the most optimised accuracy for a given FFT length. On the basis of this approach, they further present a VLSI implementation of area-efficient and high-precision FFT processor, which can perform power-of-two FFT from 32 to 8192 points. By using the SMIC 0.13 μm process, the area of the proposed FFT processor is 27 mm 2 with a maximum operating frequency of 400 MHz. When the FFT processor is configured to perform 8192-point FFT at 40 MHz, the signal-to-quantisation-noise ratio is up to 53.28 dB and the power consumption measured by post-layout simulation is 35.7 mW.

Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array

“…Table 1 provides the performance comparison values of the proposed method with existing methods like CORDIC‐based FFT [22], floating point FFT [31, 32] and reconfigurable radix‐2 2 FFT [33]. FFT size, area, power consumption, frequency rate and execution time are some performance parameters considered to compare the result of the proposed method.…”

“…In UMA, is processed repeatedly. A final step is needed to transform the result back to [31, 32]. Given the below algorithm explains the radix‐r UMA method Algorithm 1 (see Fig.…”

Energy efficient VLSI architecture of real‐valued serial pipelined FFT

“…This reduces the area‐complexity of FFT architecture, but successive use of memory banks and processing elements lead to higher power consumption. On the other hand, pipelined FFT architectures [9–12] have the advantage of lower power with higher throughput over the memory‐based FFT architectures [13–17]. They are further categorised on the basis of samples processed per iteration, namely, serial (or single‐path) and parallel (or multi‐path) architectures.…”