Video DSP architecture for MPEG2 codec

A High-Performance Architecture with a Macroblock-Level-Pipeline for MPEG-2 Coding

“…In order to make a real-time MPEG-2 video coder, each process must be executed within the permitted time for an MB (MB latency) [24]. This time is: T MB ϭ 24.69 s, for the resolutions and frame rate selected in MP@ML (720 ϫ 480 ϫ 30 or 720 ϫ 576 ϫ 25).…”

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

“…Even the implementations of complex and computationally-intensive tasks, for instance video compression applications, migrate from custom processors to programmable platforms (e.g. [19] and [24]). To reach a performance-and power-optimized implementation point, the main bottleneck is to manipulate the computational complexity of data-intensive applications.…”

UWICL: A Multi-Layered Parallel Image Computing Library for Single-Chip Multiprocessor-based Time-Critical Systems

“…If the A + B * C computation were implemented without using library routines, we could easily eliminate the additional loop control and data movement, and dispense with additional temporary space needed. Even though individual routines are well optimized, the composition overhead may limit the usefulness of library routines significantly, especially when the library routines are designed to support time-critical applications for specific DSPs.Furthermore, the single-layered API is not appropriate to utilize the available resources effectively in highly integrated processors such as a single-chip multiprocessor with large on-chip memory [4][5][6][7]. In such processors, because of the large penalty associated with accessing off-chip memory, it may be more efficient to apply a sequence of primitive operations to one section of input…”