A High-Performance Architecture with a Macroblock-Level-Pipeline for MPEG-2 Coding

Fernández, José M.; Moreno, Félix; Meneses, Juan

doi:10.1006/rtim.1996.0034

Cited by 10 publications

(2 citation statements)

References 16 publications

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“…High performance parallel and pipelined architecture has been used in implementation of several types of image and sound processing with tight real time constraints in System-on-a-Chip (SoC) design [1,2,3,11]. In a system with pipelined architecture, each task periodically receives input data from its predecessor tasks, performs its computation and sends output data to its successor tasks.…”

Section: Introductionmentioning

confidence: 99%

A real time budgeting method for module-level-pipelined bus based system using bus scenarios

Tanimoto

Yamaguchi

Nakata

et al. 2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus based system while satisfying given end-to-end real-time constraints of the entire system such as throughput and latency constraints. In this paper, we define a bus scenario representing a set of possible execution sequences of tasks and bus transfers executed in a bus based system. Then we propose a method for deriving real time budgets of all the tasks running in parallel and pipelined fashion from the pair of a system configuration (such as bus topology) and a bus scenario. In deriving such real time budgets, we consider computational complexity of each task, the amount of bus transfers and bus arbitration policies (e.g. fixed priority or time divided round robin based arbitration). We show that the proposed method is effective for designing several bus based systems such as MPEG decoders.

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Section: Introductionmentioning

confidence: 99%

A real time budgeting method for module-level-pipelined bus based system using bus scenarios

Tanimoto

Yamaguchi

Nakata

et al. 2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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show abstract

“…• En la primera de ellas [Fer98] se lleva a cabo un estudio de la carga computacional requerida para la ejecución del lazo de codificación (transformada discreta del coseno, cuantificación, cuantificación inversa y transformada discreta del coseno inversa) y se propone la arquitectura MViP {MPEG Video Processor) [FMM96] como una solución flexible y eficiente para su realización.…”

Section: Justificación Y Objetivos De La Tesisunclassified

Arquitectura versátil para la codificación de vídeo multi-estándar: aportaciones metodológicas para el diseño de sistemas reutilizables y sistemas en un chip

González¹

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Decisión inter/intra 2.2.13 Régimen binario de salida del codificador 2.2.14 Los modos opcionales 2.4.1.1 Los objetos audiovisuales 2.4.1.2 La escena audiovisual 2.4.1.3 Procedimiento de acceso a los contenidos MPEG-4 Arquitectura versátil para la codificación de video multi-estándar: aportaciones metodológicas para el diseño de sistemas reutilizables y sistemas en un chip 2.4.1.4 Sincronización, multiplexado y transporte de las tramas elementales 2.4.1.5 Bases de tiempos 2.4.1.6 Transporte de MPEG-4 sobre la Trama de Transporte MPEG-2 2.4.2 MPEG-4 Vídeo 2.4.2.1 Formato de las imágenes de entrada al codificador 2.4.2.2 Tipos de imagen 2.4.2.3 La trama de salida del codificador 2.4.2.4 Herramientas utilizadas en la codificación de imágenes rectangulares 2.4.2.5 Técnicas de recuperación fi-ente a errores 2.4.2.6 Selección de los diferentes modos de codificación 2.4.2.7 Régimen binario de salida del codificador 2.4.2.8 Codificación escalable 2.5 RESUMEN

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The rapid prototyping experience of an H.263 video coder onto FPGA

Garrido

Sanz

Jimenez

et al. 2005

Microprocessors and Microsystems

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A High-Performance Architecture with a Macroblock-Level-Pipeline for MPEG-2 Coding

Cited by 10 publications

References 16 publications

A real time budgeting method for module-level-pipelined bus based system using bus scenarios

A real time budgeting method for module-level-pipelined bus based system using bus scenarios

Arquitectura versátil para la codificación de vídeo multi-estándar: aportaciones metodológicas para el diseño de sistemas reutilizables y sistemas en un chip

The rapid prototyping experience of an H.263 video coder onto FPGA

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