Very Short Critical Path Implementation of AES with Direct Logic Gates

Nekado, Kenta; Nogami, Yasuyuki; Iokibe, Kengo

doi:10.1007/978-3-642-34117-5_4

Cited by 12 publications

(27 citation statements)

References 11 publications

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“…. is another redundant representation of GF [10]. Each element is represented by a root of an m-th degree irreducible polynomial, similarly to PB and NB.…”

Section: Redundantly Represented Basis (Rrb)mentioning

confidence: 99%

“…The critical delay of such an RRB-based multiplier is T A + 2T X , while those of multipliers based on non-redundant representations are T A + 3T X [10]. The gate count of the RRB-based multiplier requires only 10 AND and 25 XOR gates [10], whereas that of a PRR-based multiplier requires 25 AND and 20 XOR gates [5]. Nekado et al [10] designed a more efficient GF ((2 4 ) 2 ) inversion circuit based on RRB by utilizing the above advantage.…”

Section: Redundantly Represented Basis (Rrb)mentioning

confidence: 99%

“…According to Eqs. (24)-(28), the proposed Stage 2 requires T A + T O + T X delay, whereas the conventional structures [3,10,11,14] require at least T A + 3T X . Note that when the multiplicative unit element E(x) (= x 4 +x 3 +x 2 +x) is given as the input, the output becomes not E(x) but 1.…”

Section: Subfield Inversionmentioning

confidence: 99%

“…Stage 3 generates the final output using two GF (2 4 ) multiplication operations, where both the inputs and output are given by RRB. As stated above, the RRBbased GF (2 4 ) multiplier is known to be one of the most efficient multipliers [10].…”

Section: Final Multiplicationmentioning

confidence: 99%

“…Drolet [5] showed that the use of PRR makes it possible to select a binomial x n + 1 as a modular polynomial, which can lead to the design of small-complexity arithmetic circuits. Wu et al [16] and Nekado et al [10] showed that RRB-based designs were useful for designing efficient inversion circuits.…”

Section: Introductionmentioning

confidence: 99%

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Highly Efficient $$GF(2^8)$$ G F ( 2 8 ) Inversion Circuit Based on Redundant GF Arithmetic and Its Application to AES Design

Ueno

Homma

Sugawara

et al. 2015

Lecture Notes in Computer Science

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This paper proposes a compact and efficient GF (2 8) inversion circuit design based on a combination of non-redundant and redundant Galois Field (GF) arithmetic. The proposed design utilizes redundant GF representations, called Polynomial Ring Representation (PRR) and Redundantly Represented Basis (RRB), to implement GF (2 8) inversion using a tower field GF ((2 4) 2). In addition to the redundant representations, we introduce a specific normal basis that makes it possible to map the former components for the 16th and 17th powers of input onto logic gates in an efficient manner. The latter components for GF (2 4) inversion and GF (2 4) multiplication are then implemented by PRR and RRB, respectively. The flexibility of the redundant representations provides efficient mappings from/to the GF (2 8). This paper also evaluates the efficacy of the proposed circuit by means of gate counts and logic synthesis with a 65 nm CMOS standard cell library and comparisons with conventional circuits, including those with tower fields GF (((2 2) 2) 2). Consequently, we show that the proposed circuit achieves approximately 40 % higher efficiency in terms of area-time product than the conventional best GF (((2 2) 2) 2) circuit excluding isomorphic mappings. We also demonstrate that the proposed circuit achieves the best efficiency (i.e., area-time product) for an AES encryption S-Box circuit including isomorphic mappings. Keywords: Compact hardware implementation • GF (2 8) inversion • S-Box • AES

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“…. is another redundant representation of GF [10]. Each element is represented by a root of an m-th degree irreducible polynomial, similarly to PB and NB.…”

Section: Redundantly Represented Basis (Rrb)mentioning

confidence: 99%