2016
DOI: 10.1007/978-3-662-53140-2_26
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A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths

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Cited by 25 publications
(21 citation statements)
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“…For comparison with AES, we will use one of the more recent results from [UMHA16] where an area-speed optimized AES-128 (10 rounds) on NanGate 15nm technology runs with the speed 71.19 Gbps and has the area 17232 GE. This means that having the same design, AES-256 (14 rounds) would run with the speed of 50.85 Gbps.…”
Section: E Snow-v Reference Implementation With Simdmentioning
confidence: 99%
“…For comparison with AES, we will use one of the more recent results from [UMHA16] where an area-speed optimized AES-128 (10 rounds) on NanGate 15nm technology runs with the speed 71.19 Gbps and has the area 17232 GE. This means that having the same design, AES-256 (14 rounds) would run with the speed of 50.85 Gbps.…”
Section: E Snow-v Reference Implementation With Simdmentioning
confidence: 99%
“…Willing to consider a realistic AES implementation for exhaustive key search purposes, we refer to [38], where the authors survey the state of the art of Application-Specific Integrated Circuit (ASIC) AES implementations, employing the throughput per Gate Equivalent (GE) as their figure of merit. The most performing AES implementations are the ones proposed in [38], and require around 16ki GEs. We thus deem reasonable to estimate the computational complexity of an execution of AES as 16ki binary operations.…”
Section: Security Level Goalsmentioning
confidence: 99%
“…The system that created is based on AES, which is it very best performing algorithm in ciphering and deciphering since it doesn't need complex mathematical formula [3,10]. And it has flexibility in use because of it can used in ciphering message or images [10,11]. Also, the AES is chosen based on preforming of the algorithm.…”
Section: Introductionmentioning
confidence: 99%