Highly Efficient $$GF(2^8)$$ G F ( 2 8 ) Inversion Circuit Based on Redundant GF Arithmetic and Its Application to AES Design

Abstract

This paper proposes a compact and efficient GF (2 8) inversion circuit design based on a combination of non-redundant and redundant Galois Field (GF) arithmetic. The proposed design utilizes redundant GF representations, called Polynomial Ring Representation (PRR) and Redundantly Represented Basis (RRB), to implement GF (2 8) inversion using a tower field GF ((2 4) 2). In addition to the redundant representations, we introduce a specific normal basis that makes it possible to map the former components for the 16th and 17th powers of input onto logic gates in an efficient manner. The latter components for GF (2 4) inversion and GF (2 4) multiplication are then implemented by PRR and RRB, respectively. The flexibility of the redundant representations provides efficient mappings from/to the GF (2 8). This paper also evaluates the efficacy of the proposed circuit by means of gate counts and logic synthesis with a 65 nm CMOS standard cell library and comparisons with conventional circuits, including those with tower fields GF (((2 2) 2) 2). Consequently, we show that the proposed circuit achieves approximately 40 % higher efficiency in terms of area-time product than the conventional best GF (((2 2) 2) 2) circuit excluding isomorphic mappings. We also demonstrate that the proposed circuit achieves the best efficiency (i.e., area-time product) for an AES encryption S-Box circuit including isomorphic mappings. Keywords: Compact hardware implementation • GF (2 8) inversion • S-Box • AES

A low critical path delay structure for composite field AES S-box based on constant matrices multiplication merging

“…The low CPD structure of AES S-box proposed in this paper only take structural aspect into consideration. The CPD also can be shortened by take mixed basis [22,23].…”

“…Note that only standard basis and normal basis are discussed in this paper. The CPD also can be shortened by take special CFA technologies in [22,23]. In [22], redundantly represented basis are mixed with standard basis and normal basis.…”

“…In [22], redundantly represented basis are mixed with standard basis and normal basis. And polynomial ring representation are further added to construct composite field GF((2 4 ) 2 ) in [23]. Unlike the low CPD design strategies adopted in [22,23], we are mainly focused on the construct methods of low CPD structures for the AES S-box and InvS-box.…”

“…And polynomial ring representation are further added to construct composite field GF((2 4 ) 2 ) in [23]. Unlike the low CPD design strategies adopted in [22,23], we are mainly focused on the construct methods of low CPD structures for the AES S-box and InvS-box. As shown on Table IV, except for [22,23], our S-box and InvS-box has minimal CPD compared with previous works,.…”

“…Therefore, hardware implementations of AES S-box based on CFA have caught more attentions in current studies. Different construction schemes of composite fields have been proposed for AES S-box in previous works [12][13][14][15][16][17][18][19][20][21][22][23]. Most of these works mainly focus on reducing area cost.…”