Vertically integrated ZnO-Based 1D1R structure for resistive switching

Zhang, Yang; Duan, Ziqing; Li, Rui; Ku, Chieh-Jen; Reyes, Pavel Ivanoff; Ashrafi, Almamun; Zhong, Jiaming; Lu, Yicheng

doi:10.1088/0022-3727/46/14/145101

Cited by 35 publications

(19 citation statements)

References 27 publications

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“…The nonlinear relationship in region III was fitted using ln( I/V ) vs V 1/2 plots, as shown in the inset of Figure b. The Poole–Frenkel emission can be described by

ln true(\frac{J}{E} true) \propto q^{3 \ 2} true(π ϵ_{0} ϵ_{normalr} true)^{- 1 \ 2} {true(r k T true)}^{- 1} E^{1 \ 2}

where J is the current density, E is the electric field, T is the temperature, r is a parameter that ranges between 1 and 2 and depends on the position of the Fermi level, q is the electron charge, and ϵ i is the insulator permittivity. The results indicated that the conductive mechanism is dominated by the Poole–Frenkel emission in region III.…”

Section: Resultsmentioning

confidence: 99%

Bipolar Resistive Switching Properties of Hf_0.5Zr_0.5O₂ Thin Film for Flexible Memory Applications

Zhu

Zhou

et al. 2017

Physica Status Solidi (a)

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An Au/Ni/Hf 0.5 Zr 0.5 O 2 /Au flexible memory device fabricated on a polyethylene terephthalate substrate was studied for flexible resistive random access memory applications. A typical bipolar resistive switching behavior was revealed with an OFF/ON ratio of approximately 15. The reproducibility and uniformity were investigated using 100 repetitive write/erase cycles. The retention property did not degrade for up to 5 Â 10 4 s, and the resistive switching properties did not degrade even under bending conditions, which indicated good mechanical flexibility. The current-voltage characteristics of the memory device show a Poole-Frenkel emission conduction mechanism in the high-voltage region in the high-resistance state, while in the low-voltage region, the Ohmic contact and space charge limit current responded to the low-resistance state and high-resistance state, respectively. Combined with the conductance mechanism, the resistive switching behavior is attributed to conductive filaments forming and rupturing due to oxygen vacancies migrating under the external driving electric field.

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“…The nonlinear relationship in region III was fitted using ln( I/V ) vs V 1/2 plots, as shown in the inset of Figure b. The Poole–Frenkel emission can be described by

ln true(\frac{J}{E} true) \propto q^{3 \ 2} true(π ϵ_{0} ϵ_{normalr} true)^{- 1 \ 2} {true(r k T true)}^{- 1} E^{1 \ 2}

Section: Resultsmentioning

confidence: 99%

Bipolar Resistive Switching Properties of Hf_0.5Zr_0.5O₂ Thin Film for Flexible Memory Applications

Zhu

Zhou

et al. 2017

Physica Status Solidi (a)

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“…Анализ литературных данных показал, что существует несколько механизмов мемристорного эффекта в оксидах металлов [4,5,14,15]. Для объяснения результатов исследований мемристорного эффекта в структуре Ti/ZnO/Pt, представленных в данной работе, можно использовать механизм, связанный с формированием наноразмерных каналов проводимости [14,15].…”

Section: результаты и их обсуждениеunclassified

“…при приложении внешнего электрического поля выше порогового значения. По значению сопротивления выделяют два состояния пленки: состояние с большим сопротивлением (HRS) и состояние с меньшим сопротивлением (LRS) [4][5][6][7][8][9].…”

Section: Introductionunclassified

“…Оксид цинка (ZnO) является одним из наиболее перспективных материалов для создания элементов энергонезависимой резистивной памяти (RRAM) [4][5][6], что обусловлено его электрофизическими свойствами: широкой запрещенной зоной, химической стабильностью высокими теплопроводностью и температурой плавления, пьезо-и пироэффектами, биологической совместимостью и т. д. [7].…”

Section: Introductionunclassified

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Исследование мемристорного эффекта в нанокристаллических пленках ZnO

Smirnov¹,

Tominov²,

Avilov³

et al. 2019

Физика И Техника Полупроводников

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Представлены результаты экспериментальных исследований мемристорного эффекта и влияния режимов отжига на электрофизические свойства нанокристаллических пленок оксида цинка, полученных методом импульсного лазерного осаждения. Показана возможность получения нанокристаллических пленок оксида цинка методом импульсного лазерного осаждения в широком диапазоне электрических (удельное сопротивление от 1.44 · 10 −5 до 8.06 · 10 −1 Ом · см) и морфологических (шероховатость от 0.43 ± 0.32 до 6.36 ± 0.38 нм) параметров, за счет использования послеростового отжига в атмосфере кислорода (давление 10 −1 и 10 −3 Торр, температура 300 и 800 • C, длительность от 1 до 10 ч). Показано, что нанокристаллическая пленка оксида цинка толщиной 58 ± 2 нм проявляет стабильный мемристорный эффект, слабозависящий от ее морфологии -приложение напряжения −2.5 и +4 В приводит к переключению между состояниями с сопротивлением 3.3 ± 1.1 · 10 9 и 8.1 ± 3.4 · 10 7 Ом соответственно. Полученные результаты могут быть использованы при разработке конструкций и технологических процессов изготовления элементов резистивной памяти на основе мемристорного эффекта, а также приборов опто-, микро-, наноэлектроники и наносистемной техники.

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“…Our baseline NVM-cache replaces the SRAM-based L2 cache with RRAM of similar area size; a memory die consists of eight subarrays, one of which a small fraction of memristor island by constructing 512x512 matrix [13]. Since the feature size of SRAM is around 125 F 2 [19] (while that of RRAM around 4 F 2 [20]), it can offer around 30x bigger storage capacity than the SRAM-based cache. To make our baseline NVM-cache denser, we proposed 3D-stacked NVM-cache, which piles up four memory layers, and each of them has a single pre-decode logic [16], [17].…”

mentioning

confidence: 99%

Integrating 3D Resistive Memory Cache into GPGPU for Energy-Efficient Data Processing

Zhang

Donofrio

Shalf

2015

2015 International Conference on Parallel Architecture and Compilation (PACT)

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General purpose graphics processing units (GPUs) have become a promising solution to process massive data by taking advantages of multithreading. Thanks to thread-level parallelism, GPU-accelerated applications improve the overall system performance by up to 40 times [1], [2], compared to CPU-only architecture. However, data-intensive GPU applications often generate large amount of irregular data accesses, which results in cache thrashing and contention problems [11], [12]. The cache thrashing in turn can introduce a large number of off-chip memory accesses, which not only wastes tremendous energy to move data around on-chip cache and off-chip global memory, but also significantly limits system performance due to many stalled load/store instructions [18], [21].In this work, we redesign the shared last-level cache (LLC) of GPU devices by introducing non-volatile memory (NVM), which can address the cache thrashing issues with low energy consumption. Specifically, we investigate two architectural approaches, one of each employs a 2D planar resistive random-access memory (RRAM) as our baseline NVM-cache and a 3D-stacked RRAM technology [14], [15]. Our baseline NVM-cache replaces the SRAM-based L2 cache with RRAM of similar area size; a memory die consists of eight subarrays, one of which a small fraction of memristor island by constructing 512x512 matrix [13]. Since the feature size of SRAM is around 125 F 2 [19] (while that of RRAM around 4 F 2 [20]), it can offer around 30x bigger storage capacity than the SRAM-based cache. To make our baseline NVM-cache denser, we proposed 3D-stacked NVM-cache, which piles up four memory layers, and each of them has a single pre-decode logic [16], [17].Based on our experiment analysis, we observe that the baseline NVM-cache already can minimize off-chip memory accesses under many modern GPU computing applications. Therefore, in this work, we reduce the area size of LLC by employing our 3D-stacked NVM-cache architecture but it is still able to offer the storage capacity as same as what the baseline NVM-cache provides. This turns out that the onchip LLC with our 3D-stacked NVM-cache only requires 1/4 room space, which allows modern GPU systems to employ a bigger L1D cache. Our two RRAM-integrated GPU architectures enable the systems to perform data processing without sacrifices on thread-level parallelism (imposed by thread block throttling on a streaming processor) and to address the issues brought by cache thrashing and off-chip memory accesses. (a) IPC. (b) Last-level cache misses. Figure 1: Performance improvement. (a) DRAM dynamic energy. (b) LLC energy. Figure 2: Energy efficiency.To evaluate the performance of SRAM-based LLC and our NVM-cache approaches, we used CACTI 6.5 [3] and NVSim 1.0 [4], respectively, and implemented them into GPGPUSim 3.2.2 [5]. For energy measurement, we also used GPUWattch [6]. In this primary evaluation, we selected ten applications from Polybench [7], Rodinia [8], Mars [9], and Parboil [10]. Fig. 1(a) shows that, our baseline NVMcache and 3D-stack...

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Vertically integrated ZnO-Based 1D1R structure for resistive switching

Cited by 35 publications

References 27 publications

Bipolar Resistive Switching Properties of Hf_0.5Zr_0.5O₂ Thin Film for Flexible Memory Applications

Bipolar Resistive Switching Properties of Hf_0.5Zr_0.5O₂ Thin Film for Flexible Memory Applications

Исследование мемристорного эффекта в нанокристаллических пленках ZnO

Integrating 3D Resistive Memory Cache into GPGPU for Energy-Efficient Data Processing

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Vertically integrated ZnO-Based 1D1R structure for resistive switching

Cited by 35 publications

References 27 publications

Bipolar Resistive Switching Properties of Hf0.5Zr0.5O2 Thin Film for Flexible Memory Applications

Bipolar Resistive Switching Properties of Hf0.5Zr0.5O2 Thin Film for Flexible Memory Applications

Исследование мемристорного эффекта в нанокристаллических пленках ZnO

Integrating 3D Resistive Memory Cache into GPGPU for Energy-Efficient Data Processing

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Bipolar Resistive Switching Properties of Hf_0.5Zr_0.5O₂ Thin Film for Flexible Memory Applications

Bipolar Resistive Switching Properties of Hf_0.5Zr_0.5O₂ Thin Film for Flexible Memory Applications