Vertical Transistor With n-Bridge and Body on Gate for Low-Power 1T-DRAM Application

Lin, Jyi-Tsong; Lin, Hsi-Hsiang; Chen, Yijie; Yu, Cyuan-You; Kranti, Abhinav; Lin, Chih-Chia; Lee, Wei-Han

doi:10.1109/ted.2017.2766563

Cited by 8 publications

(8 citation statements)

References 19 publications

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“…Optimizing L CG /L T is advantageous as RFET exhibits higher retention (6.1 s for L S /L T = 0.4 (L CG /L T = 0.3), 8.7 s for L S /L T = 0.6 (L CG /L T = 0.5), 3.95 s for L S /L T = 0.8 (L CG /L T = 0.4)) as compared to previously reported data. RFET based 1T-DRAM with L T = 50 nm (L S /L T = 0.6 and L CG /L T = 0.4) exhibits a good RT of 175 ms (>64 ms) at 85 • C which shows potential for extending [27], twin gate (2G) [50], and L-shaped (L) [28] tunnel FET (TFET), Z 2 FET [31], Ultrathin BOX [51], impact ionization MOS (IMOS) [30], n-bridge and body-on-gate (BOG) FET [52], electron-bridge channel (ECB) FET [53], 3G-RFET [32], and 2G-RFET [33] based 1T-DRAM with our results at 85 • C. multifunctional attributes of RFET through the implementation of standalone 1T-DRAM.…”

Section: Benchmarkingmentioning

confidence: 99%

“…Figures 15(a [27], TFETs (twin gate (2G) [50], and L-shaped (L) [28]), Z 2 FET [31], Ultra-thin BOX [51], I-MOS [30], n-bridge and body-on-gate (BOG) vertical FET [52], Electron-bridge channel (ECB) FET [53], and RFETs [32,33]). Optimizing L CG /L T is advantageous as RFET exhibits higher retention (6.1 s for L S /L T = 0.4 (L CG /L T = 0.3), 8.7 s for L S /L T = 0.6 (L CG /L T = 0.5), 3.95 s for L S /L T = 0.8 (L CG /L T = 0.4)) as compared to previously reported data.…”

Section: Benchmarkingmentioning

confidence: 99%

“…Figure 15.Comparison of (a) RT with SM, and (b) RT with L T for junctionless (JL) FET[27], twin gate (2G)[50], and L-shaped (L)[28] tunnel FET (TFET), Z 2 FET[31], Ultrathin BOX[51], impact ionization MOS (IMOS)[30], n-bridge and body-on-gate (BOG) FET[52], electron-bridge channel (ECB) FET[53], 3G-RFET[32], and 2G-RFET[33] based 1T-DRAM with our results at 85 • C.…”

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confidence: 99%

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A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

Nirala¹,

Semwal²,

Kranti³

2022

Semicond. Sci. Technol.

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Capacitorless dynamic memory (1T-DRAM) operation in a reconfigurable transistor (RFET) is critically governed by different lengths associated with the architecture. These lengths consisting of ungated region (LUG), control gate (LCG), polarity gate (LPG), storage region length (LS), and total length (LT) can be sensitive to the fabrication process, and hence, critical for 1T-DRAM. This work presents an insightful critique of the above mentioned lengths for realising optimal 1T-DRAM performance. It is shown that RFET with highest values of LS/LT and LCG/LT shows good short channel immunity but does not necessarily ensure enhanced 1T-DRAM metrics. Results indicate that for a fixed LT, retention time (RT) can vary over a wide range (550 ms to 8.7 s) depending on the values of LS/LT and LCG/LT, and hence, appropriate optimization is imperative. The work contributes towards better understanding and optimizing LCG/LT to ensure improved 1T-DRAM metrics in terms of enhanced retention (> 64 ms), acceptable sense margin (> 6 µA/µm), current ratio (> 104) with low values of read (2 ns) and write (1 ns) time to further extend multi-functional facets of nanoscale RFETs for memory applications. In addition, the effect of traps, process sensitivity, reduced number of voltage levels, and disturbance caused by shared word line/bit line are also analysed in this work. Results indicate that state ‘0’ of the cell sharing bit line (BL) with the selected cell is strongly affected by BL disturbance. Word line (WL) disturbance primarily impacts state ‘1’ of the cell sharing WL with selected cell (only for write 1 and read operations).

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Section: Benchmarkingmentioning

confidence: 99%

Section: Benchmarkingmentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

Nirala¹,

Semwal²,

Kranti³

2022

Semicond. Sci. Technol.

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“…This method is different from impact ionization or gate-induced drain leakage (GIDL) used in the previous 1T DRAM devices. [36][37][38][39][40][41][42]…”

Section: Device Operationsmentioning

confidence: 99%

Reliability improvement of 1T DRAM based on feedback transistor by using local partial insulators

Jang

Ansari

Kım

et al. 2021

Jpn. J. Appl. Phys.

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This paper proposes a one-transistor dynamic random-access memory (1 T DRAM) with local partial insulator (LPI) to increase data retention time. Proposed 1 T DRAM cell has improved retention characteristics because LPIs inhibit stored carrier movement with a high energy barrier. Definition of retention time in the proposed 1 T DRAM is introduced at hold “0” state. Device optimization with parameter variation is investigated with device simulation. As the barrier length increases, retention characteristics can be improved but it also causes a decrease in the I1/I0 current ratio. An increase in LPI length can improve the retention characteristics but reduce the I1/I0 current ratio. It was confirmed that the retention characteristics were improved as the hold bias was decreased. Finally, the retention characteristics were optimized when the LPI was precisely formed at the junction boundary.

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“…However, planar 1T-DRAM still exhibits poor retention time. Therefore, various structures and methods for improving the memory characteristic have been investigated [6][7][8][9][10][11][12][13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure

Lee

Park

et al. 2022

Nanomaterials

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In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

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Vertical Transistor With n-Bridge and Body on Gate for Low-Power 1T-DRAM Application

Cited by 8 publications

References 19 publications

A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

Reliability improvement of 1T DRAM based on feedback transistor by using local partial insulators

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure

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