Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands

Abstract

A variable latency adder (VLA) reduces average addition time by using speculation: the exact arithmetic function is replaced by an approximated one, that is faster and gives correct results most of the times. When speculation fails, an error detection and correction circuit gives the correct result in the following clock cycle. Previous papers investigate VLAs based on Kogge-Stone, Han-Carlson or carry select topologies, speculating that carry propagation involves only a few consecutive bits. In several applications using 2's complement representation, however, operands have a Gaussian distribution and a nontrivial portion of carry chains can be as long as the adder size. In this paper we propose five novel VLA architectures, based on Brent-Kung, Ladner-Fisher, Sklansky, Hybrid Han-Carlson, and Carry increment parallel-prefix topologies. Moreover, we present a new efficient error detection and correction technique, that makes proposed VLAs suitable for applications using 2's complement representation. In order to investigate VLAs performances, proposed architectures have been synthesized using the UMC 65 nm library, for operand lengths ranging from 32 to 128 bits. Obtained results show that proposed VLAs outperform previous speculative architectures and standard (non-speculative) adders when high-speed is required

Optimized VLSI Architecture of HEVC Fractional Pixel Interpolators with Approximate Computing

“…As for the Luma case, the Chroma architecture takes advantage of the increase in performance granted by the reduction of N tap : Given a × 32 block, a −34.9% of energy reduction is achieved when considering the 2-tap filter instead of the legacy 4-tap one (Table 8). Most importantly, Table 7 shows that, differently from he H.C. and GeAr adders in the Luma case, the Adder presented in [16] shows for the Chroma case a huge improvement in terms of area reduction (−28.37%) and f max • pel max /A ratio (+40, 6%) at the minor cost of a performance reduction (−4.39%) and a power consumption increase (+1.58%).…”

“…In this work, we stem from the architecture in [13] and we coherently integrate it, for the first time, with other state-of-the-art techniques [10,[15][16][17] and an alternative scheduling algorithm. The result obtained is a new optimized interpolation filter architecture, where important optimizations are introduced: (i) The amount of memory is drastically reduced, (ii) multipliers are substituted with adders by extending the optimized structure presented in [10] for legacy filters to the case of lower order filters.…”

“…• The topology in [16], which uses outer Brent-Kung layers and inner Ladner-Fischer layers. This solution is able to shorten the critical path delay with respect to the tree of prefix operators.…”

“…The [16] topology is applied to the Chroma Legacy architecture as it shows the best improvements in performance, at the cost of a negligible area overhead and power dissipation. On the other hand, the Han-Carlson one is applied to the Luma Approximate because it guarantees the highest precision.…”

Accuracy enhancement of equal segment based approximate adders

“…Note that in (a), (c) and (e), the left y-axis corresponds to ER and the right y-axis corresponds to MRED Fig. 7 Generalised architecture of ACAs/VLSAs [33] IET Comput. Digit.…”