Variable-Latency Floating-Point Multipliers for Low-Power Applications

Kuang, Shiann-Rong; Wang, Jiun-Ping; Hong, Hua-Yi

doi:10.1109/tvlsi.2009.2025167

Cited by 15 publications

(14 citation statements)

References 10 publications

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“…[38] proposed a variable-latency floating-point multiplier architecture which was compliant with IEEE 754-1985 and was deemed suitable for low-power applications (see Figure XII). The multiplier architecture of [39] splits the mantissa multiplier into the upper and lower components, and predicts the, sticky bit, carry bit, and mantissa product from the upper part. In the event that the prediction is correct the computation of the lower part is disabled and the rounding operation is simplified, hence allowing the system to consume less power [38] The system of [39] computed the biased exponent by the summation of both biased exponents of inputs using binary adders followed by subtraction of the bias.…”

Section: Double Precision Floating-point Multiplicationmentioning

confidence: 99%

“…The multiplier architecture of [39] splits the mantissa multiplier into the upper and lower components, and predicts the, sticky bit, carry bit, and mantissa product from the upper part. In the event that the prediction is correct the computation of the lower part is disabled and the rounding operation is simplified, hence allowing the system to consume less power [38] The system of [39] computed the biased exponent by the summation of both biased exponents of inputs using binary adders followed by subtraction of the bias. Source: Data from [39] The proposed multiplier was implemented in Verilog and synthesized using Synopsys Design Compiler with TSMC CMOS standard cell library.…”

Section: Double Precision Floating-point Multiplicationmentioning

confidence: 99%

See 1 more Smart Citation

Comparative Review of Floating-Point Multiplier Systems

George¹,

Tobago²

2019

IJHIT

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This paper presents a comprehensive comparative review of existing floating-point multiplier systems. The study focuses on single, double, quadruple and multi-precision floating point multiplier architectures and seeks to identify engineering techniques involved in their development. A comparison of the performance of these systems in terms of metrics such as path delay, hardware utilization and even power consumption in some case are carried out. Weaknesses in the systems reviewed along with possible gaps in the area of research are identified. This paper also serves to identify several recommendations and considerations for the development of a multi-precision floating point multiplier system capable of treating with the weaknesses of multiplier systems identified.

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Section: Double Precision Floating-point Multiplicationmentioning

confidence: 99%

Section: Double Precision Floating-point Multiplicationmentioning

confidence: 99%

Comparative Review of Floating-Point Multiplier Systems

George¹,

Tobago²

2019

IJHIT

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“…In the IEEE-754 floating point format [1] there are two precisions are available, one is the single precision and another one is the double precision. In the single precision there are 32-bits and in double precision there are 64-bits are available.…”

Section: Ieee-754 Floating Point Formatmentioning

confidence: 99%

Area efficient run time reconfigurable architecture for double precision multiplier

Shanmugapriyan¹,

Sivanandam²

2015

2015 IEEE 9th International Conference on Intelligent Systems and Control (ISCO)

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In many application Floating point Arithmetic is basic building blocks such as Scientific, digital signal processing and numeric. In this Floating point Arithmetic, Multiplication is most commonly used method. This multipliers are going to discussing about the double precision multiplier. This double precision operation is performed in the form of IEEE-754 FP (floating point) standard format. The first architecture is the novel truncated block multiplication, with one unit in the last place (ULP) precision from IEEE-754 FP standard format. The second architecture is used to regain the lost of accuracy from the first design with some extra hardware logic. The third architecture is used to perform either single precision or double precision. The Vedic multiplication algorithm is used in all the architecture for the purpose of multiplication process.

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“…There are a few previous works that leverage quality as a design knob for reducing power consumptions in floating point multipliers [5][6] [8][9] [10]. Most of these works use intuitive bit truncations and voltage scaling that results in a relatively large percentage of power/energy savings.…”

Section: Related Workmentioning

confidence: 99%

A low-power accuracy-configurable floating point multiplier

Zhang

Lach

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Floating point multiplication is one of the most frequently used arithmetic operations in a wide variety of applications, but the high power consumption of the IEEE-754 standard floating point multiplier prohibits its implementation in many low power systems, such as wireless sensors and other battery-powered embedded systems, and limits performance scaling in high performance systems, such as CPUs and GPGPUs for scientific computation. This paper presents a lowpower accuracy-configurable floating point multiplier based on Mitchell's Algorithm. Post-layout SPICE simulations in a 45nm process show same-delay power reductions up to 26X for single precision and 49X for double precision compared to their IEEE-754 counterparts. Functional simulations on six CPU and GPU benchmarks show significantly better power reduction vs. quality degradation trade-offs than existing bit truncation schemes.

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Variable-Latency Floating-Point Multipliers for Low-Power Applications

Cited by 15 publications

References 10 publications

Comparative Review of Floating-Point Multiplier Systems

Comparative Review of Floating-Point Multiplier Systems

Area efficient run time reconfigurable architecture for double precision multiplier

A low-power accuracy-configurable floating point multiplier

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