Comparative Review of Floating-Point Multiplier Systems

Abstract

This paper presents a comprehensive comparative review of existing floating-point multiplier systems. The study focuses on single, double, quadruple and multi-precision floating point multiplier architectures and seeks to identify engineering techniques involved in their development. A comparison of the performance of these systems in terms of metrics such as path delay, hardware utilization and even power consumption in some case are carried out. Weaknesses in the systems reviewed along with possible gaps in the area of research are identified. This paper also serves to identify several recommendations and considerations for the development of a multi-precision floating point multiplier system capable of treating with the weaknesses of multiplier systems identified.

Hardware Implementation of a High Efficiency and High-Speed Squaring Architecture

“…The drastic growth in digital technology and the expansion of digital signal processing (DSP) applications increase the demand for high-speed processing, which is possible by the high throughput arithmetic operations [1]. Arithmetic Logic Units (ALUs) are the vital blocks of processors that perform various arithmetic operations such as addition, subtraction, division, multiplication, and squaring [2].…”