FPGA Implementation of Power Efficient Floating Point Fused Multiply-Add Unit

Mounika, K.; Ramana, P. V.

doi:10.1109/csnt51715.2021.9509678

Cited by 1 publication

(4 citation statements)

References 6 publications

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“…Experiment 1. The aim is to find out approximately how many decimal digits can be encapsulated in the proposed short floating point formats and thus check the validity of equations ( 7) and (8). Theses formats are fp16, fp16-20 and fp16-24.…”

Section: Methodsmentioning

confidence: 99%

“…The theoretical number of digits that can be encapsulated into short floating point formats using truncation and rounding can be consulted in Table Table 4. The theoretical were obtained using formulas (7) and (8). The values of Table Table 4 can be compared with the results obtained from encoding-decoding process in Table Table 5.…”

Section: Methodsmentioning

confidence: 99%

“…In [8], the author realizes the implementation of a fusion of the multiplication and accumulation circuits following the linear form of the IEEE-754 standard to save resources in the FPGA.…”

Section: Of 18mentioning

confidence: 99%

“…To calculate the number of fractional decimal digits that can be encapsulated in a floating point format regarding truncation process regard the formula (8), below:…”

Section: Number Of Equivalent Decimal Digitsmentioning

confidence: 99%

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Short hybrid floating-point formats based on 16-bit for FPGA-based arithmetic implementations

Ibarra-Carrillo,

Molina-Lozano,

Montiel-Pérez

2023

Preprint

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Nowadays, there are implemented devices whose purpose is to perform massive computations by saving resources at the time they reduce the latency of arithmetic operations. These devices are usually GPUs, FPGAs and other specialised devices such as "Coral". Neural networks, digital filters and numerical simulators take advantage of the massively parallel operations of such devices. One way to reduce the amount of resources used is to limit the size of the registers that store data. This has led to the proliferation of numeric formats with a length of less than 32 bits, known as short floating point or SFP. We have developed several SFP’s for use in our neural network accelerator design, allowing for different levels of accuracy. We use a 16-bit format for data transfer and different formats can be used simultaneously for internal operations. The internal operations can be performed in 16-bit, 20-bit and 24-bit. The use of registers larger than 16-bit allows the preservation of fractional information while increasing precision. By leveraging some of the FPGA’s arithmetic resources, our design outperforms designs implemented from scratch and is competitive with specialized arithmetic circuits already implemented in the FPGA.

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Section: Of 18mentioning

confidence: 99%

“…To calculate the number of fractional decimal digits that can be encapsulated in a floating point format regarding truncation process regard the formula (8), below:…”

Section: Number Of Equivalent Decimal Digitsmentioning

confidence: 99%

See 2 more Smart Citations

Short hybrid floating-point formats based on 16-bit for FPGA-based arithmetic implementations

Ibarra-Carrillo,

Molina-Lozano,

Montiel-Pérez

2023

Preprint

View full text Add to dashboard Cite

show abstract

FPGA Implementation of Power Efficient Floating Point Fused Multiply-Add Unit

Cited by 1 publication

References 6 publications

Short hybrid floating-point formats based on 16-bit for FPGA-based arithmetic implementations

Short hybrid floating-point formats based on 16-bit for FPGA-based arithmetic implementations

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