Variability-aware design space exploration of embedded memories

Abstract

With scaling of process technologies and worsening of process variations, embedded memories are susceptible to a large number of failure mechanisms making it hard to achieve high yield. In this paper, by bringing together architecture and circuit-level exploration tools, we analyse the impact of process variations on static random access memory (SRAM) cell stability and determine the impact of SRAM failures on memory functional yield. We then detail the importance of repair mechanisms such as error correcting codes (ECC) and redundancy on improving yield subject to constraints set on power and area. Finally, we show that a design paradigm orthogonal to traditional repair mechanisms involving redefinition of the yield criterion by accepting memories with failures is a promising candidate for improving yield without incurring additional overheads.

Adaptive error correction coding scheme for computations in the noisy min-sum decoder

“…The major difference between the density evolution analysis of the nominal min-sum decoder and that of the robust min-sum decoder is in the linear transformation (2). Given the coding scheme introduced in Sec.…”

“…Such memory errors may be caused by voltage over-scaling, semiconductor process variation, electromagnetic interference, etc. [2]. We assume that the BSCs for different memory cells are independent but have the same cross-over (bit-flipping) probability ρ, and that the logic gates computing the messages are noise-free.…”

Energy vs. Reliability Trade-offs Exploration in Biomedical Ultra-Low Power Devices

“…Extra Bits/W ord = Sign Bit + Mask ID Size = 1 + log 2 (Data Size) bits (2) DREAM is able to correct multiple errors located in the series of MSBs highlighted by the mask. In fact, an additional data bit is always protected because the most-significant bit of the data part not covered by the mask is always set to the inverted value of the data sign bit; therefore, the position of this bit in the data-word can be specified by the mask ID and then inverted by a simple NOT gate (Set one bit block in Fig.…”

“…Therefore, to provide fair comparisons, all the EMTs are tested reusing the same set of error locations/mappings. The amount of permanent errors or stuck-at faults injected depends on the Bit Error Rate (BER) [2], obtained profiling the memory for each voltage level for the selected technology node (32 nm) with low-power memory cells.…”

“…In general, the lower the voltage is, the more energy, delay and area overheads have to be introduced in hardware (HW), to guarantee error-free operation [2]. For this reason, system designers now focus on software (SW) robustness exploration.…”