ACOCO: Adaptive Coding for Approximate Computing on Faulty Memories

Huang, Chu-Hsiang; Li, Yao; Dolecek, Lara

doi:10.1109/tcomm.2015.2481898

Cited by 13 publications

(12 citation statements)

References 34 publications

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“…2σ 2 represent the water level, the ground level, the groundflattening term, and the water depth, respectively. Compared with (19), we observe that (25) has an additional ground-flattening term log η b . By solving KKT conditions, we show that…”

Section: B Speed Maximizationmentioning

confidence: 81%

Generalized Water-filling for Source-aware Energy-efficient SRAMs

Kim

Kang

Varshney

et al. 2018

IEEE Trans. Commun.

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Conventional low-power static random access memories (SRAMs) reduce read energy by decreasing the bit-line voltage swings uniformly across the bit-line columns. This is because the read energy is proportional to the bit-line swings. On the other hand, bit-line swings are limited by the need to avoid decision errors especially in the most significant bits. We propose a principled approach to determine optimal non-uniform bit-line swings by formulating convex optimization problems. For a given constraint on mean squared error of retrieved words, we consider criteria to minimize energy (for low-power SRAMs), maximize speed (for high-speed SRAMs), and minimize energy-delay product.These optimization problems can be interpreted as classical water-filling, ground-flattening and waterfilling, and sand-pouring and water-filling, respectively. By leveraging these interpretations, we also propose greedy algorithms to obtain optimized discrete swings. Numerical results show that energyoptimal swing assignment reduces energy consumption by half at a peak signal-to-noise ratio of 30dB for an 8-bit accessed word. The energy savings increase to four times for a 16-bit accessed word. I. INTRODUCTIONVon Neumann computing architectures separate memory units from computing units so there is frequent data access that consumes enormous energy. Since static random access memories (SRAMs) access requires more energy than arithmetic operations [1], SRAM access energy accounts for the significant part of the total energy consumption in many information processing This work was supported in part by Systems on Nanoscale Information fabriCs (SONIC), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA. arXiv:1710.07153v3 [cs.IT] 29 Nov 2017 formulate convex optimization problems whose objectives are as follows: C1. Minimize energy (low-power SRAMs), C2. Maximize speed (high-speed SRAMs), C3. Minimize energy-delay product (EDP).Solutions to these convex problems yield optimal performance that is theoretically attainable.By casting read access for SRAMs as communication over parallel channels, we investigate the fundamental trade-offs between physical resources (energy, delay, and EDP) and a fidelity (MSE) constraint.In addition, we provide generalized water-filling interpretations for our optimal solutions. This follows since accessing a B-bit word is equivalent to communicating information through B parallel channels. In classical water-filling, the ground represents the noise levels of parallel channels [20], [21]. On the other hand, the importance of each bit position determines the ground level in our optimization problems. Each optimization problem has its own interpretation depending on its objective function: water-filling (C1), ground-flattening and water-filling (C2), and sand-pouring and water-filling (C3), respectively. We also observe interesting connections between our problems and variants on water-filling such as constant-power water-filling [22],[23] and mercury/water-filling [24]. Also, we show that the proposed ...

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Section: B Speed Maximizationmentioning

confidence: 81%

Generalized Water-filling for Source-aware Energy-efficient SRAMs

Kim

Kang

Varshney

et al. 2018

IEEE Trans. Commun.

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“…The techniques we survey often involve computation on noisy inputs or data processing in the presence of noise in much the same way research in communication systems and information theory considers communication over a noisy channel. As one recent example of work that could be viewed as either traditional information theory and communication systems research or approximate computing, Huang et al [80] present a simple yet effective coding scheme that uses a combination of a lossy source/channel coding to protect against hardware errors for iterative statistical inference.…”

Section: Communications and Storage Systemsmentioning

confidence: 99%

“…Early examples of such application-aware codes can be found in the work of Huang et al [80] which proposes a redundancy-free adaptive code that can correct errors in data retrieved from potentially faulty cells. The technique relies on an application-specific cost function and an input-adaptive coding scheme that pairs a source encoder that introduces modest distortion, with a channel encoder that adds redundant bits to protect the distorted data against errors.…”

Section: Application-aware Source and Channel Coding Across The Hardware Stackmentioning

confidence: 99%

Exploiting Errors for Efficiency

et al. 2020

Self Cite

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When a computational task tolerates a relaxation of its specification or when an algorithm tolerates the effects of noise in its execution, hardware, system software, and programming language compilers or their runtime systems can trade deviations from correct behavior for lower resource usage. We present, for the first time, a synthesis of research results on computing systems that only make as many errors as their end-to-end applications can tolerate. The results span the disciplines of computer-aided design of circuits, digital system design, computer architecture, programming languages, operating systems, and information theory. Rather than over-provisioning the resources controlled by each of these layers of abstraction to avoid errors, it can be more efficient to exploit the masking of errors occurring at one layer and thereby prevent those errors from propagating to a higher layer. We demonstrate the potential benefits of end-to-end approaches using two illustrative examples. We introduce a formalization of terminology that allows us to present a coherent view across the techniques traditionally used by different research communities in their individual layer of focus. Using this formalization, we survey tradeoffs for individual layers of computing systems at the circuit, architecture, operating system, and programming language levels as well as fundamental information-theoretic limits to tradeoffs between resource usage and correctness.

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“…We noticed that a similar adaptive coding scheme for approximate computing with faulty storage has been proposed in [22]. In [22], an adaptive message coding scheme on faulty min-sum LDPC decoders is mentioned.…”

Section: Existing Adaptive Messages Coding Schemementioning

confidence: 99%

“…In [22], an adaptive message coding scheme on faulty min-sum LDPC decoders is mentioned. In detail, when the messages were written into RAMs, if the MSB was 1, the last two LSBs were neglected, while the corresponding memory addresses were used for a (3, 1) repetition coding on the sign bit.…”

Section: Existing Adaptive Messages Coding Schemementioning

confidence: 99%

Design and Analysis of Adaptive Message Coding on LDPC Decoder with Faulty Storage

Yin

2018

Wireless Communications and Mobile Computing

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Unreliable message storage severely degrades the performance of LDPC decoders. This paper discusses the impacts of message errors on LDPC decoders and schemes improving the robustness. Firstly, we develop a discrete density evolution analysis for faulty LDPC decoders, which indicates that protecting the sign bits of messages is effective enough for finite-precision LDPC decoders. Secondly, we analyze the effects of quantization precision loss for static sign bit protection and propose an embedded dynamic coding scheme by adaptively employing the least significant bits (LSBs) to protect the sign bits. Thirdly, we give a construction of Hamming product code for the adaptive coding and present low complexity decoding algorithms. Theoretic analysis indicates that the proposed scheme outperforms traditional triple modular redundancy (TMR) scheme in decoding both threshold and residual errors, while Monte Carlo simulations show that the performance loss is less than 0.2 dB when the storage error probability varies from 10 −3 to 10 −4 .

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ACOCO: Adaptive Coding for Approximate Computing on Faulty Memories

Cited by 13 publications

References 34 publications

Generalized Water-filling for Source-aware Energy-efficient SRAMs

Generalized Water-filling for Source-aware Energy-efficient SRAMs

Exploiting Errors for Efficiency

Design and Analysis of Adaptive Message Coding on LDPC Decoder with Faulty Storage

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