Vancouver rocks

Turner, R; Page, J.J.; Klassen, M; Vadis, H Quo; Jensen, Aage

doi:10.4095/211534

Cited by 3 publications

(3 citation statements)

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“…The MoonGen [51] traffic generator is exploited to generate and inject background traffic at 40 Gbps into the switch, while the target encrypted traffic data is simultaneously replayed as pcap files using Tcpreplay [52]. The background traffic is included in the experiments in order to have the switch operate at all times on high-throughput traffic and increase the realism of the evaluation, however, as shown in Figure 1, only the target encrypted traffic is classified by the in-switch RF model.…”

Section: A Hardware Setupmentioning

confidence: 99%

Encrypted Traffic Classification at Line Rate in Programmable Switches with Machine Learning

Akem,

Fraysse,

Fiore

2024

NOMS 2024-2024 IEEE Network Operations and Management Symposium

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Encrypted Traffic Classification (ETC) has become an important area of research with Machine Learning (ML) methods being the state-of-the-art. However, most existing solutions either rely on offline ETC based on collected network data or on online ETC with models running in the control plane of Software-Defined Networks (SDN), all of which do not run at line rate and would not meet latency requirements of timesensitive applications in modern networks. This work leverages recent advances in data plane programmability to achieve realtime ETC in programmable switches at line rate, with high throughput and low latency. The proposed solution comprises (i) an ETC-aware Random Forest (RF) modelling process where only features based on packet size and packet arrival times are used, and (ii) an encoding of the trained RF model into production-grade P4-programmable switches. The performance of the proposed in-switch ETC framework is evaluated using 3 encrypted traffic datasets with experiments in a real-world testbed with Intel Tofino switches, in the presence of background traffic at 40 Gbps. Results show how the solution achieves high classification accuracy of up to 95%, with sub-microsecond delay, while consuming on average less than 10% of total available switch hardware resources.

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Section: A Hardware Setupmentioning

confidence: 99%

Encrypted Traffic Classification at Line Rate in Programmable Switches with Machine Learning

Akem,

Fraysse,

Fiore

2024

NOMS 2024-2024 IEEE Network Operations and Management Symposium

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“…The switches run Open Network Linux (ONL) and Intel's Software Development Environment (SDE) version 9.7.0. We developed a Python controller on top of the Barefoot Runtime Interface (BRI) to automatically perform the initial configuration of the switch, including the mapping of RF models that are trained with Scikit-Learn libraries as described in Section III-E. We then use 100Gbps connections to inject traffic into the switch from the server, by replaying pcap traces via Tcpreplay [43]. Figure 7e portrays the testbed in a rackmount configuration.…”

Section: A Hardware Setupmentioning

confidence: 99%

Flowrest: Practical Flow-Level Inference in Programmable Switches with Random Forests

Akem,

Gucciardo,

Fiore

2023

IEEE INFOCOM 2023 - IEEE Conference on Computer Communications

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“…The test scenario is the same as the one shown in Figure 18, although this time the NTP traffic generator is enabled. The generator uses the tcpreplay tool [50] to inject NTP network traffic in the LAN at a controlled data rate. It should be noticed that the LAN bandwidth used at the maximum NTP load tested is below 20 Mbps and it is far from the full-duplex 200 Mbps bandwidth of the standard switched 100 Mbps Ethernet LAN used in the setup.…”

Section: Performance Under Loadmentioning

confidence: 99%

High-Performance Time Server Core for FPGA System-on-Chip

et al. 2019

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This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in contrast to state-of-the-art high-performance time server equipment. Therefore, this core provides a valuable time server solution for a wide range of emerging embedded and distributed network applications such as the Internet of Things and the smart grid, at a fraction of the cost and footprint of current discrete and embedded solutions.

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Vancouver rocks

Cited by 3 publications

References 0 publications

Encrypted Traffic Classification at Line Rate in Programmable Switches with Machine Learning

Encrypted Traffic Classification at Line Rate in Programmable Switches with Machine Learning

Flowrest: Practical Flow-Level Inference in Programmable Switches with Random Forests

High-Performance Time Server Core for FPGA System-on-Chip

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