Validating PowerPC microprocessor custom memories

Krishnamurthy, Narayanan; Martin, Andrew K.; Abadir, Magdy S.; Abraham, Jacob A.

doi:10.1109/54.895007

Cited by 27 publications

(30 citation statements)

References 15 publications

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“…Notice that the proofs take only a few minutes to replay. This is in stark contrast with traditional equivalence checking methods [5], [7] that can take hours for verifying industrial memories. The reason is that the models are parameterized, and the verification makes use of deduction rather than state exploration, ameliorating state explosion.…”

Section: Resultsmentioning

confidence: 60%

“…Note that the bug is at the interface of two components. Since spice simulation targets individual components, such bugs typically go undetected [7], [8].…”

Section: Resultsmentioning

confidence: 99%

“…In particular, switch-level analyzers such as anamos [5] and its variants [6], [7] represent the state of the art in the abstraction of SRAM memories built with CMOS transistors. The key insight for such models is that transistors can be effectively abstracted as on-off switches from the perspective of their use in designs (such as memories) that implement digital behavior.…”

Section: A Deficiencies In Switch-level Modelsmentioning

confidence: 99%

“…Formalization of transistor circuits has chiefly focused on developing switch-level analyzers such as sls [20], mossim-ii [1], and anamos [5]. This enabled verification of regular CMOS-based digital circuits [5], [7].…”

Section: Related Workmentioning

confidence: 99%

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Modeling and verification of industrial flash memories

Ray

Bhadra²,

Portlock³

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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Abstract-We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate devices, which preclude the use of traditional switch-level abstractions for their verification. We circumvent this problem through behavioral abstractions, which allow formalization of the behaviors of the design as interacting state machines. Behavioral abstractions are agnostic to transistor type, making them suitable for formalizing flash memories. We have verified industrial flash memory implementations based on both floating gate and split gate technologies. Our work provides the first formal functional verification results for industrial flash memories.

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Section: Resultsmentioning

confidence: 60%

“…Note that the bug is at the interface of two components. Since spice simulation targets individual components, such bugs typically go undetected [7], [8].…”

Section: Resultsmentioning

confidence: 99%

Section: A Deficiencies In Switch-level Modelsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Modeling and verification of industrial flash memories

Ray

Bhadra²,

Portlock³

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

View full text Add to dashboard Cite

show abstract

“…Past SET-based techniques could usually be applied for verifying individual array blocks [3,4,5]. With special symbolic encoding techniques, it can also be efficient for verifying arrays which are content addressable in nature [6].…”

Section: Introductionmentioning

confidence: 99%

Enhanced symbolic simulation for efficient verification of embedded array systems

Feng

Wang

Cheng

et al. 2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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Abstract-In the past, Symbolic Trajectory Evaluation (STE) was shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD sizes would often blow up. In this paper, we propose using a "dual-rail" symbolic simulation scheme to facilitate the application of STE proof methodology for verifying array systems. The proposed scheme implicitly partitions a given design into control domain and datapath domain, and symbolic simulation is carried out on both domains. With this scheme, the run-time OBDD sizes during the symbolic simulation for each domain can be limited. We demonstrate the effectiveness of our approach by verifying the Memory Management Unit (MMU) in Motorola high-performance microprocessors. The verification of MMU as a whole was not possible before because of the OBDD size blow-up problem when an ordinary symbolic simulator was used in the STE proof process.

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Using Abstract Specifications to Verify PowerPC™ Custom Memories by Symbolic Trajectory Evaluation

Bhadra

Martin

Abraham

et al. 2001

Lecture Notes in Computer Science

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We present a methodology in which the behavior of a switch level device is specified using abstract parameterized regular expressions. These specifications are used to generate a finite automaton representing an abstraction of the behavior of a block of memory comprised of a set of such switch level devices. The automaton, in conjunction with an Efficient Memory Model [1], [2] for the devices, forms a symbolic simulation model representing an abstraction of the array core embedded in a larger design under analysis. Using Symbolic Trajectory Evaluation, we check the equivalence between a register transfer level description and a schematic description augmented with abstract specifications for one of the custom memories embedded in the MPC7450 PowerPC processor.

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Validating PowerPC microprocessor custom memories

Abstract: Address Data in Read enable Write enable C1 clock Data in Read/write control logic Address decode logic Data conditioning logic Sense-amp outputs column MUX Figure 15. Custom memory.

Cited by 27 publications

References 15 publications

Modeling and verification of industrial flash memories

Modeling and verification of industrial flash memories

Enhanced symbolic simulation for efficient verification of embedded array systems

Using Abstract Specifications to Verify PowerPC™ Custom Memories by Symbolic Trajectory Evaluation

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