UV-hardened high-modulus CVD-ULK material for 45-nm node Cu/low-k interconnects with homogeneous dielectric structures

Furusawa, Takeshi; Miura, Naruhisa; Matsumoto, Masahiro; Goto, Kazuya; Hashii, Shinobu; Fujiwara, Y.; Yoshikawa, Kazunori; Yonekura, Kazumasa; Asano, Yoshinobu; Ichiki, Tsutomu; Kawanabe, Naoki; Matsuzawa, Toshihiro; Matsuura, M.

doi:10.1109/iitc.2005.1499918

Cited by 6 publications

(7 citation statements)

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“…Therefore, doping hydrocarbon atom groups to polymer networks as cross-links is expected to be a key to obtaining low-k and high-modulus films, 8) as the hydrocarbon cross-links would contribute to film strengthening. Several experimental studies showed the mechanical strengthening 9,10) and property balance improvement 11) (as shown in Fig. 1) of SiOCH films with hydrocarbon crosslinks, although the effect of hydrocarbon bridging on film properties has not been investigated sufficiently.…”

Section: Introductionmentioning

confidence: 99%

Carbon-Doped Silicon Oxide Films with Hydrocarbon Network Bonds for Low-k Dielectrics: Theoretical Investigations

Tajima

Ohno

Hamada

et al. 2007

jjap

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We have computationally explored the chemical structures of carbon-doped silicon oxide (SiOCH) films that give the smallest dielectric constant (k) under the required mechanical strength for low-k dielectrics. The focus of this study is on the SiOCH structures that have hydrocarbon components in the polymer network as cross-links. It has been found that SiOCH films of small dielectric constants can have improved mechanical strengths if the hydrocarbon components form cross-links, instead of the terminal methyl groups in the conventional structure. The calculated results suggest that SiOCH films of ideal structures can have substantially smaller dielectric constants than films of current interconnect technology with the same mechanical strengths.

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Section: Introductionmentioning

confidence: 99%

Carbon-Doped Silicon Oxide Films with Hydrocarbon Network Bonds for Low-k Dielectrics: Theoretical Investigations

Tajima

Ohno

Hamada

et al. 2007

jjap

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“…Low-k interlayer dielectric (ILD) materials are replacing traditional SiO 2 in new high-performance devices. However, low-k ILD materials have a Young's modulus of less than 20 GPa, [1][2][3][4][5] which is much lower than that of SiO 2 (70 GPa), and weaker adhesion strength than other insulating films. [6][7][8][9] In particular, chip-package interaction failures of the multilayer interconnects during assembly processes are of concern.…”

Section: Introductionmentioning

confidence: 99%

“…[6][7][8][9] In particular, chip-package interaction failures of the multilayer interconnects during assembly processes are of concern. 1,[10][11][12][13][14][15][16][17] During a thermal cycle test, significant mechanical stress is generated in a chip owing to thermal mismatch between the package and the chip. This can result in a delamination failure of the ILD layer at the chip corner.…”

Section: Introductionmentioning

confidence: 99%

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Stress Analysis for Chip–Package Interaction of Cu/Low-k Multilayer Interconnects

Kumagai¹,

Ohta²,

Fujisawa

et al. 2010

Jpn. J. Appl. Phys.

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Delamination failure of a low-k interlayer dielectric (ILD) layer of Cu/low-k multilayer interconnects during a thermal cycle test was investigated by mechanical stress simulation. A three-dimensional (3D) multilevel modeling method was used to analyze the stress that occurred in a fine-scale film stack in a large-scale package. The maximum stress occurred at the low-k/cap film interface that was located at the bottom surface of the low-k ILD layer. This maximum-stress interface coincides with the interface where the delamination occurred. Using this method, the effects of the number of ILD layers, the Young's modulus of the ILD, and the package type on the failure were investigated. This method is useful for reducing delamination failure.

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“…11) Degradation of TDDB immunity, which is particularly serious in Cu/low-k interconnects (for example refs. [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19], is caused by a wedge-shaped LER, as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

Characterization of Line-Edge Roughness in Cu/Low-k Interconnect Pattern

Yamaguchi¹,

Ryuzaki²,

Takeda³

et al. 2008

jjap

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To establish a method of measuring interconnect line-edge roughness (LER), low-k line patterns were observed and electric field concentration was simulated on the basis of observation results. Wedge-shaped LERs were observed at the edges of low-k lines, and the bottom and the top widths of the average wedge feature were 60 and 7 nm (or smaller), respectively. Simulation showed that LER causes serious electric field concentration, which may cause the degradation of time-dependent dielectric breakdown (TDDB) lifetime at 100-nm-pitch Cu/low-k interconnects. The maximum electric field strength depends on the conventional LER metric 3R q , but depends more strongly on the wedge angle, the curvature of the tip. That is, other metrics such as wedge angle can predict fatal electric field concentration caused by LER than the conventional metric 3R q .

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UV-hardened high-modulus CVD-ULK material for 45-nm node Cu/low-k interconnects with homogeneous dielectric structures

Cited by 6 publications

References 0 publications

Carbon-Doped Silicon Oxide Films with Hydrocarbon Network Bonds for Low-k Dielectrics: Theoretical Investigations

Carbon-Doped Silicon Oxide Films with Hydrocarbon Network Bonds for Low-k Dielectrics: Theoretical Investigations

Stress Analysis for Chip–Package Interaction of Cu/Low-k Multilayer Interconnects

Characterization of Line-Edge Roughness in Cu/Low-k Interconnect Pattern

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