Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits

Abstract-Static timing analysis is instrumental in efficiently verifying a design's temporal behavior to ensure correct functionality at the required frequency. This paper addresses static timing analysis in the presence of cross talk for circuits containing levelsensitive latches, typical in high-performance designs. The paper focuses on two problems. First, coupling in a sequential circuit can occur because of the proximity of a victim's switching input to any periodic occurrence of the aggressor's input switching window. This paper shows that only three consecutive periodic occurrences of the aggressor's input switching window must be considered. Second, an arrival time in a sequential circuit is typically computed relative to a specific clock phase. The paper proposes a new phase shift operator to align the aggressor's three relevant switching windows with the victim's input signals. This paper solves the static analysis problem for level-clocked circuits iteratively in polynomial time, and it shows an upper bound on the number of iterations equal to the number of capacitors in the circuit. The contributions of this paper hold for any discrete overlapping coupling model. The experimental results demonstrate that eliminating false coupling allows finding a smaller clock period at which a circuit will run.

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“…1) Compute the latch-to-latch, PI to latch, and latch-to-PO minimum and maximum delays as outlined in [19]. The run time is dominated by O…”

Section: Algorithmmentioning

confidence: 99%

Static timing analysis for level-clocked circuits in the presence of crosstalk

Hassoun

Cromer²,

Calvillo-Gamez³

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…It was observed in [5] that retiming and clock skew scheduling are discrete and continuous optimizations with the same effect. The equivalence between retiming and skew scheduling has been used in prior researches [7], [8], [9], [10]. Although retiming is a powerful sequential optimization technique, its practical usage is limited due to its impact on the verification process, e.g.…”

Section: Introductionmentioning

confidence: 99%

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network

Mohammadzadeh¹,

Mirsaeedi²,

Jahanian³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract. Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizing such clock scheduler may be considerable if registers are placed without considering assigned skews. Focusing on this issue, in this paper, we propose a skew scheduling-aware register placement algorithm that enables clock tree optimization by considering domains assigned to registers in placement. Our experimental results show that the proposed approach remarkably decreases clock wire length and clock network power consumption at the cost of a slight increase in total wire length.

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“…Transform the input arrival times of FFs to clock skews. (2) Use the skew-retiming equivalence relation [7] to realize the clock skew assigned to FFs.…”

mentioning

confidence: 99%

Minimum-area sequential budgeting for FPGA

Yeh

Marek-Sadowska

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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The constraint-based approach to timing-driven placement requires delay budgeting to define the delay upper bounds for nets. While most of the previous delay-budgeting works have been focused on optimizing combinational circuits, the work in [9] introduces sequential budgeting, which combines budgeting and retiming to optimize sequential circuits better. However, the formulation in [9] does not consider flip-flop (FF) minimization, which is important in practical applications. Here, we propose a new sequential budgeting algorithm, C-SBGT, that not only controls the FF count, but also can be solved more efficiently compared to [9]. Our formulation has fewer constraints than [9] and the procedure to realize retiming is also simpler. Our experiments show that our new min-area sequential budgeting algorithm produces a good trade-off between the area and budgeting optimization goals, as well as improving the timing of previous sequential budgeting method by 12%.

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Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits

Cited by 67 publications

References 15 publications

Static timing analysis for level-clocked circuits in the presence of crosstalk

Static timing analysis for level-clocked circuits in the presence of crosstalk

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network

Minimum-area sequential budgeting for FPGA

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