Utilizing parallelism of TMR to enhance power efficiency of reliable ASIC designs

Sämrow, Hagen; Cornelius, Claas; Salzmann, Jakob; Tockhorn, Andreas; Timmermann, Dirk

doi:10.1109/icces.2010.5674862

Cited by 2 publications

(3 citation statements)

References 18 publications

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“…For instance, p COMP = 0 means that the modules run exclusively in parallel, whereas p COMP = 1 denotes that the modules operate solely in the compare phase. The duration of the compare phase has been set to an appropriate level so that the design is able to detect the faults in most cases [20]. In Figure 5 all power values are calculated in relation to the conventional TMR design.…”

Section: B Simulation Results Without Fault Injectionmentioning

confidence: 99%

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Functional enhancements of TMR for power efficient and error resilient ASIC designs

Sämrow

Cornelius

Gorski

et al. 2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work introduces a Low Power Redundant (LPR) design solution that targets the power penalty of TMR implementations. This is done by enhanced and new functional runtime capabilities for error detection and operation control. By exploiting the inherent modularity and parallelism of TMR, the LPR solution applies additional control logic to switch dynamically between compare phases (to indicate faults and their locations) and parallel operation (with reduced operation frequency). This allows power optimized circuit operation with full support for the treatment of permanent faults. Simulation results on different ALU implementations show a decrease of power consumption of up to 60 % compared to conventional TMR. Furthermore, different strategies for the switching between operation modes are introduced that enable power efficient system operation in the presence of permanent physical defects. Moreover, significant reliability improvements are also achieved due to the adaptive use of the redundant modules.

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Section: B Simulation Results Without Fault Injectionmentioning

confidence: 99%

“…This also allows a seamless integration of the proposed design modification into an automated EDA workflow. In [20] we presented a related approach where the design has been toggled between a TMR and a standalone mode. We have reached power savings up to 50 %, but we have not delved into flexible strategies when faults are detected.…”

Section: Introductionmentioning

confidence: 99%

Functional enhancements of TMR for power efficient and error resilient ASIC designs

Sämrow

Cornelius

Gorski

et al. 2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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“…It is, however, quite expensive in terms of area and power. An enhanced TMR approach is presented in [121,122] that harnesses TMR's parallelism by switching between a low-frequency parallel mode and the TMR mode when needed, leading to power savings.…”

Section: Triple Modular Redundancy (Tmr)mentioning

confidence: 99%

Scalable techniques for extending lifetime reliability of manycore systems

Rathore¹

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First, I want to thank my supervisor Prof. Thambipillai Srikanthan for giving me the opportunity of undertaking a Ph.D. under his sage guidance. His vision and most insightful advice have shaped this endeavor into a fruitful culmination-from choosing the topic to developing ideas and identifying any missing pieces to thesis writing. The motivation and kind support that he has provided have enabled the smooth continuation of the Ph.D., especially around the birth of my second daughter. This thesis would not have completed without the phenomenal support provided by my mentor Dr. Vivek Chaturvedi through his excellent guidance and constant help. The many technical discussions and numerous writing revisions have contributed profoundly to my research. A special note of thanks goes to Dr. Muhammad Shafique, whose exceptional guidance into research writing and the brainstorming into the formulation of some critical ideas have been vital for this thesis. Also, I thank Dr. Amit K. Singh for the most timely and critical review of my work, and Dr. Lam Siew-Kei for introducing me to the research field. I am grateful to Rohith R., the intern who developed the simulator. I thank Mr. Jeremiah, the administrative staff member of HESL, for the swift technical support. This journey was enlivened by the joyful presence of my friends Yan, Serene, Surabhi, Indira, Bhavan, Akhila, and Nruthya. My senior, Dr. Kavitha, has been a never-exhausting source of motivation. My colleague Kalindu has always been a high helping hand and provided me with insights. With my colleagues Deshya and Thilina, I shared many light moments and also a deep understanding. Peilan was my empath who understood the struggles of student-mothers. Meiqing uplifted me with her sweet demeanor. Kratika always made me positive. Dr. Jagadeesh was ever available with great advice. The role my husband, Virender Singh, and my daughters Prisha and Mitali in this thesis cannot be entirely expressed in words. Their sacrifice and love I can xi xii never repay. The positivity, comfort, fun, smile, and laughter they bring always rejuvenated me after a hard day. My husband's encouraging words, care, and understanding, as well as the technical discussions with him, made this journey possible. I thank Prisha for her loving smile and kindness, and Mitali for the zeal and strength she imparted. Also, the unconditional support of my parents-in-law and their highly understanding and helpful nature is almost not heard of elsewhere. My helpers have been the support-system allowing me to juggle work and personal responsibilities. The foundation of values and courage laid by my parents has been fundamental. My mother, Mrs. Pushpa Rathore has encouraged me throughout the journey. My brother and sisters have given me comfort and a listening ear whenever needed. I would forever remain indebted to Daaji, global guide of Heartfulness meditation system, for what has been given spiritually, equipping me with lightness, serenity, and positivity. My trainer and friend, Sis. Sheenah Hamid, has contr...

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Utilizing parallelism of TMR to enhance power efficiency of reliable ASIC designs

Cited by 2 publications

References 18 publications

Functional enhancements of TMR for power efficient and error resilient ASIC designs

Functional enhancements of TMR for power efficient and error resilient ASIC designs

Scalable techniques for extending lifetime reliability of manycore systems

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