Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform

Zabihi, Masoud; Zhao, Zhengyang; Dc, Mahendra; Chowdhury, Zamshed I.; Resch, Salonik; Peterson, T.; Karpuzcu, Ulya R.; Wang, Jianping; Sapatnekar, Sachin S.

doi:10.1109/isqed.2019.8697377

Cited by 31 publications

(18 citation statements)

References 12 publications

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“…Reducing access transistor resistance is important for today's technology but is not a significant factor for advanced technologies. For the SHE-CRAM [13], a similar analysis shows that interconnect parasitics are not significant as the current values are much smaller.…”

Section: Discussionmentioning

confidence: 88%

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Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

Zabihi

Sharma

Mankalale

et al. 2020

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell-and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations. INDEX TERMS In-memory computing, spin-transfer torque computational random access memory (STT-CRAM), spintronics.

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Section: Discussionmentioning

confidence: 88%

“…In this case, in column i, N parallel structures, each consisting of series connections of R y , R via , R MTJ 1 i , and R T , connect through R x to the output cell, modeled as a series connection of R T and R MTJ 2 . We generalize (13) to…”

Section: B Thevenin Model For N-input Gatesmentioning

confidence: 99%

Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

Zabihi

Sharma

Mankalale

et al. 2020

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…The long-term STT specification is based on projections from the literature [18]. SHE-MTJ specification comes from [19]. We model access transistors after 22-nm (HP) PTM [20].…”

Section: Phase 2 (Similarity Score Computation)mentioning

confidence: 99%

Spintronic In-Memory Pattern Matching

Chowdhury

Khatamifard

Zhao

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Traditional Von Neumann computing is falling apart in the era of exploding data volumes as the overhead of data transfer becomes forbidding. Instead, it is more energy-efficient to fuse compute capability with memory where the data reside. This is particularly critical to pattern matching, a key computational step in large-scale data analytics, which involves repetitive search over very large databases residing in memory. Emerging spintronic technologies show remarkable versatility for the tight integration of logic and memory. In this article, we introduce SpinPM, a novel high-density, reconfigurable spintronic in-memory pattern matching spin-orbit torque (SOT)-specifically spin Hall effect (SHE)-substrate, and demonstrate the performance benefit SpinPM can achieve over conventional and near-memory processing systems. INDEX TERMS Computational random access memory, pattern matching, processing in memory, spin Hall effect (SHE) magnetic tunnel junction (MTJ).

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“…At the same time, the convolutional networks implemented in our study are an order of magnitude larger than the network proposed in Reference [32]. Our baseline spintronic PIM substrate, CRAM, was introduced in Reference [7] and evaluated for simple and very small-scale (non-binary) NN (limited to a single-neuron digit recognizer and 2D convolution, specifically) in Reference [46]. As we cover in Section 2.2, this basic memory cell and array structure cannot support BNN acceleration without modification.…”

Section: Related Workmentioning

confidence: 99%

Pimball

Resch

Khatamifard

Chowdhury

et al. 2019

ACM Trans. Archit. Code Optim.

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Neural networks span a wide range of applications of industrial and commercial significance. Binary neural networks (BNN) are particularly effective in trading accuracy for performance, energy efficiency, or hardware/software complexity. Here, we introduce a spintronic, re-configurable in-memory BNN accelerator, PIMBALL: Processing In Memory BNN AcceL(L)erator, which allows for massively parallel and energy efficient computation. PIMBALL is capable of being used as a standard spintronic memory (STT-MRAM) array and a computational substrate simultaneously. We evaluate PIMBALL using multiple image classifiers and a genomics kernel. Our simulation results show that PIMBALL is more energy efficient than alternative CPU-, GPU-, and FPGA-based implementations while delivering higher throughput. CCS Concepts: • Computer systems organization → Other architectures;

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Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform

Cited by 31 publications

References 12 publications

Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

Spintronic In-Memory Pattern Matching

Pimball

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