Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

Zabihi, Masoud; Sharma, Arvind Kumar; Mankalale, Meghna G.; Chowdhury, Zamshed I.; Zhao, Zhengyang; Resch, Salonik; Karpuzcu, Ulya R.; Wang, Jian Ping; Sapatnekar, Sachin S.

doi:10.1109/jxcdc.2020.2985314

Cited by 10 publications

(13 citation statements)

References 12 publications

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“…Figure 3 shows how a NAND gate can be performed inside the array. V loдic must be within a speciied range for each type of logic operation [110,154].…”

Section: Stt Array Architecturementioning

confidence: 99%

See 1 more Smart Citation

Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions

Resch

Khatamifard

Chowdhury

et al. 2022

ACM Trans. Embed. Comput. Syst.

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Beyond edge devices can operate outside the reach of the power grid and without batteries. Such devices can be deployed in large numbers in regions which are difficult to access. Using machine learning, these devices can solve complex problems and relay valuable information back to a host. Many such devices deployed in low earth orbit can even be used as nano-satellites. Due to the harsh and unpredictable nature of the environment, these devices must be highly energy efficient, be capable of operating intermittently over a wide temperature range, and be tolerant of radiation. Here, we propose a non-volatile processing-in-memory (PIM) architecture which is extremely energy efficient, supports minimal overhead checkpointing for intermittent computing, can operate in a wide range of temperatures, and has a natural resilience to radiation.

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“…Figure 3 shows how a NAND gate can be performed inside the array. V loдic must be within a speciied range for each type of logic operation [110,154].…”

Section: Stt Array Architecturementioning

confidence: 99%

“…For example, a NAND instruction may specify that it is to be performed in CRAM array 15, with inputs in rows 7 and 9, and the output in row 12. We restrict logic operations to at most two inputs, which are shown to be reliable [110,154]. As COPY, XOR, and XNOR gates are not natively supported in CRAM, there are only 5 unique logic instructions.…”

Section: Logicmentioning

confidence: 99%

Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions

Resch

Khatamifard

Chowdhury

et al. 2022

ACM Trans. Embed. Comput. Syst.

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“…Using two transistors per cell significantly increases the area per cell from 0.0012 µm 2 [63] to 0.038 15 µm 2 [96]. However, two transistors are essential for removing cross-bar sneak paths [47], which would significantly increase energy consumption.…”

Section: Architecture Designmentioning

confidence: 99%

“…Hence, it is ideal to have 4,096 rows in order to store all elements and enable parallel element-wise homomorphic multiplications and additions. However, due to parasitic bitline/rowline resistance and capacitance, arrays are limited to 1024x1024 [96]. Hence, we use 16 rows of computation arrays, where each array is 512x512.…”

Section: Architecture Designmentioning

confidence: 99%

Towards Homomorphic Inference Beyond the Edge

Resch¹,

Chowdhury²,

Cılasun³

et al. 2021

Preprint

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Beyond edge devices can function off the power grid and without batteries, enabling them to operate in difficult to access regions. However, energy costly long-distance communication required for reporting results or offloading computation becomes a limitation. Here, we reduce this overhead by developing a beyond edge device which can effectively act as a nearby server to offload computation. For security reasons, this device must operate on encrypted data, which incurs a high overhead. We use energy-efficient and intermittent-safe in-memory computation to enable this encrypted computation, allowing it to provide a speedup for beyond edge applications within a power budget of a few milliWatts.

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“…In [15], a framework is presented to incorporate the effects of nonidealities in 2D resistive crossbar performance. In [16], an analytical approach is developed to study the effects of the parasitic of wires for the implementation on spintronics computational RAM.…”

Section: Introductionmentioning

confidence: 99%

Exploring the Feasibility of Using 3-D XPoint as an In-Memory Computing Accelerator

Zabihi

Resch

Cılasun

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This paper describes how 3D XPoint memory arrays can be used as in-memory computing accelerators. We first show that thresholded matrix-vector multiplication (TMVM), the fundamental computational kernel in many applications including machine learning, can be implemented within a 3D XPoint array without requiring data to leave the array for processing. Using the implementation of TMVM, we then discuss the implementation of a binary neural inference engine. We discuss the application of the core concept to address issues such as system scalability, where we connect multiple 3D XPoint arrays, and power integrity, where we analyze the parasitic effects of metal lines on noise margins. To assure power integrity within the 3D XPoint array during this implementation, we carefully analyze the parasitic effects of metal lines on the accuracy of the implementations. We quantify the impact of parasitics on limiting the size and configuration of a 3D XPoint array, and estimate the maximum acceptable size of a 3D XPoint subarray.

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Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

Cited by 10 publications

References 12 publications

Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions

Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions

Towards Homomorphic Inference Beyond the Edge

Exploring the Feasibility of Using 3-D XPoint as an In-Memory Computing Accelerator

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