Using a configurable processor generator for computer architecture prototyping

Solomatnikov, Alex; Firoozshahian, Amin; Shacham, Ofer; Asgar, Zain; Wachs, Megan; Qadeer, Wajahat; Richardson, Stephen; Horowitz, Mark

doi:10.1145/1669112.1669159

Cited by 9 publications

(5 citation statements)

References 42 publications

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“…Our experiments use a CMP platform based on Tensilica's extensible RISC cores [2][39] [40]. This baseline implementation defines the gap we seek to bridge between general-purpose computing and ASIC efficiencies.…”

Section: Experimental Methodologymentioning

confidence: 99%

Understanding sources of inefficiency in general-purpose chips

Hameed

Qadeer

Wachs

et al. 2010

Proceedings of the 37th Annual International Symposium on Computer Architecture

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326

106

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Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance and energy efficiency. This paper explores the sources of these performance and energy overheads in general-purpose processing systems by quantifying the overheads of a 720p HD H.264 encoder running on a general-purpose CMP system. It then explores methods to eliminate these overheads by transforming the CPU into a specialized system for H.264 encoding. We evaluate the gains from customizations useful to broad classes of algorithms, such as SIMD units, as well as those specific to particular computation, such as customized storage and functional units.The ASIC is 500x more energy efficient than our original fourprocessor CMP. Broadly, applicable optimizations improve performance by 10x and energy by 7x. However, the very low energy costs of actual core ops (100s fJ in 90nm) mean that over 90% of the energy used in these solutions is still "overhead". Achieving ASIC-like performance and efficiency requires algorithm-specific optimizations. For each sub-algorithm of H.264, we create a large, specialized functional unit that is capable of executing 100s of operations per instruction. This improves performance and energy by an additional 25x and the final customized CMP matches an ASIC solution's performance within 3x of its energy and within comparable area.

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Section: Experimental Methodologymentioning

confidence: 99%

Understanding sources of inefficiency in general-purpose chips

Hameed

Qadeer

Wachs

et al. 2010

Proceedings of the 37th Annual International Symposium on Computer Architecture

Self Cite

326

106

View full text Add to dashboard Cite

show abstract

“…Such portability is important when profiling tunable codes on reconfigurable cache architectures. We cannot profile every code on every cache configuration [43].…”

Section: Portable Characteristicsmentioning

confidence: 99%

Inferred Models for Dynamic and Sparse Hardware-Software Spaces

Lee

2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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Diverse software and heterogeneous hardware pose new challenges in systems and architecture management. Managers benefit from improving introspective capabilities, which provide data across a spectrum of platforms, from software and datacenter profilers to performance counters and canary circuits. Despite this wealth of data, management has become more difficult as sophisticated decisions are demanded.To address these challenges, we present modeling strategies for integrated hardware-software analysis. These strategies include (i) identifying shared software behavior; (ii) quantifying that behavior in a portable, microarchitecture-independent manner; (iii) inferring generalized trends with statistical regression models; and (iv) automatically constructing/updating these models as new software profiles are obtained.Models produced by these strategies are accurate for general SPEC2006 applications with median errors of 8-10%. Predicted and actual performance are strongly correlated with coefficients of ρ > 0.9. Moreover, when we exploit application semantics and domain-specific software parameters, model accuracy improves and model complexity falls. In a case study for sparse linear algebra, we present models with 5% median error and new capabilities in coordinated hardware-software tuning.

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“…The Stanford Smart Memories (SSM) research project [4]- [8] aimed to build a hardware platform supporting multiple programming models by relying on a flexible execution and memory system architecture. Each SSM chip contains eight Tensilica processors, several modular reconfigurable memory blocks, and a programmable protocol controller.…”

Section: The Smart Memories Chipmentioning

confidence: 99%