Understanding sources of inefficiency in general-purpose chips

Hameed, Rehan; Qadeer, Wajahat; Wachs, Megan; Azizi, Omid; Solomatnikov, Alex; Lee, Benjamin C.; Richardson, Stephen; Kozyrakis, Christos; Horowitz, Mark

doi:10.1145/1815961.1815968

Cited by 326 publications

(110 citation statements)

References 22 publications

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“…Hameed et al in [16] quantify the performance and energy overheads of a H.264 encoder running on a general purpose CMP and explore methods to eliminate these overheads by adding optimizations such as SIMD units and processing units that are completely customized to implement H.264. In our work we build on the superior performance efficiency that customization provides and explore a wider range of design points.…”

Section: Related Workmentioning

confidence: 99%

“…In our work we build on the superior performance efficiency that customization provides and explore a wider range of design points. SIMD units and tightly coupled custom units described in [16] are two of the design points we study. Our main contribution is that we have designed a processor platform that can implement a large class of algorithms.…”

Section: Related Workmentioning

confidence: 99%

“…Recent industry and academic efforts have focused on processor customization as a solution to improve performance and energy efficiency, also taking advantage of rising transistor count. It has been well established that customizing processor data paths and data storage elements to suit the data flow of specific applications, which subsequently reduces overheads due to instruction fetching and decoding, can lead to improved performance and energy efficiencies [16,27,5,15,8,14,22]. Most of these heterogeneous architectures work based on the principle of executing sequential code on a general purpose core and offloading computation with data-level parallelism onto specialized energy efficient functional units.…”

Section: Introductionmentioning

confidence: 99%

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Exploring architectural heterogeneity in intelligent vision systems

Chandramoorthy

Tagliavini

Irick

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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Limited power budgets and the need for high performance computing have led to platform customization with a number of accelerators integrated with CMPs. In order to study customized architectures, we model four customization design points and compare their performance and energy across a number of computer vision workloads. We analyze the limitations of generic architectures and quantify the costs of increasing customization using these micro-architectural design points. This analysis leads us to develop a framework consisting of low-power multi-cores and an array of configurable micro-accelerator functional units. Using this platform, we illustrate data flow and control processing optimizations that provide for performance gains similar to custom ASICs for a wide range of vision benchmarks.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Exploring architectural heterogeneity in intelligent vision systems

Chandramoorthy

Tagliavini

Irick

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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“…The level-one data cache (L1D) uses up to 25% of the total power of a processor [6,9]. The processor's overall power is increased by inefficiencies in the data memory hierarchy such as unnecessary cache line transfers and stall cycles caused by cache misses.…”

Section: Introductionmentioning

confidence: 99%

Improving data access efficiency by using a tagless access buffer (TAB)

Bardizbanyan

Gavin²,

Whalley³

et al. 2013

Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

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The need for energy efficiency continues to grow for many classes of processors, including those for which performance remains vital. Data cache is crucial for good performance, but it also represents a significant portion of the processor's energy expenditure. We describe the implementation and use of a tagless access buffer (TAB) that greatly improves data access energy efficiency while slightly improving performance. The compiler recognizes memory reference patterns within loops and allocates these references to a TAB. This combined hardware/software approach reduces energy usage by (1) replacing many level-one data cache (L1D) accesses with accesses to the smaller, more powerefficient TAB; (2) removing the need to perform tag checks or data translation lookaside buffer (DTLB) lookups for TAB accesses; and (3) reducing DTLB lookups when transferring data between the L1D and the TAB. Accesses to the TAB occur earlier in the pipeline, and data lines are prefetched from lower memory levels, which result in a small performance improvement. In addition, we can avoid many unnecessary block transfers between other memory hierarchy levels by characterizing how data in the TAB are used. With a combined size equal to that of a conventional 32-entry register file, a four-entry TAB eliminates 40% of L1D accesses and 42% of DTLB accesses, on average. This configuration reduces data-access related energy by 35% while simultaneously decreasing execution time by 3%.

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“…However, with near-threshold supply, dim silicon designs suffer from diminishing throughput returns as the core number increases. On the other hand, customized accelerators are attracting more attention due to their orders of magnitude higher power efficiency than general-purpose processors [16,32]. Although accelerators are promising in improving performance with less power consumption, they are built for specific applications, have limited utilization in general-purpose applications, and sacrifice die area that could be used for more general-purpose cores.…”

Section: Multiprocessorsmentioning

confidence: 99%

First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems

Wang¹

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As the semiconductor industry keeps evolving at the pace predicted by Moore's Law, computer system architects are facing increasing challenges from the three major design constraints: performance, power, and reliability. Thermal constraints from a reasonable cooling cost do not scale well as technology evolves. The dwindling scaling on threshold voltage leads to a slower pace of supply voltage scaling. These two effects lead to an increasing power density in current and future technology generations. Reliability has emerged as a primary design constraint due to the smaller feature size and generally lower supply voltage for electronic devices. Transient errors caused by high-energy particle strike and voltage noises are expected to increase significantly in frequency.Performance improvement becomes more challenging for future architectures with limitations set by the power and the resilience constraints.Integration of accelerators to create heterogeneous processors is becoming more common for both power and performance reasons. However, this adds one more dimension to the design space that is already complex due to technology variants, system organizations, application's variability, and so on. Therefore, high-level models are essential for system designers to explore the design space and make decisions in a timely manner. Additionally, the three design constraints compete with each other. For example, resilience-aware techniques, such as DMR and TMR, are expensive in terms of power and performance, low-power designs usually come with a price of lower speed.Consequently, it requires system designers to make trade-offs by considering all the three design constraints at the same time.To address these challenges, we (1) propose an analytical modeling framework called Lumos that is capable of modeling power and performance for heterogeneous architectures with hardware iv v accelerators. Then we (2) use Lumos to explore the design space composed of CPU cores and accelerators, revealing important scaling trend for future heterogeneous architectures. We further (3) propose a rapid modeling framework to characterize resilience across a range of applications in DSP, and image processing domains; And finally we (4) propose an integrated framework to optimize energy-efficiency by trading off design constraints of power, performance and resilience. Acknowledgments

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Understanding sources of inefficiency in general-purpose chips

Cited by 326 publications

References 22 publications

Exploring architectural heterogeneity in intelligent vision systems

Exploring architectural heterogeneity in intelligent vision systems

Improving data access efficiency by using a tagless access buffer (TAB)

First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems

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