Unravelling complex nature of CdS/CdTe based thin film solar cells

Abstract

and high-temperature growth techniques. The wide bandgap (E g = 2.42 eV) window material, CdS was mainly grown by chemical bath deposition (CBD) and narrow bandgap (E g = 1.45 eV) absorber material, CdTe was grown by over 14 different methods [1]. High efficiencies were achieved by the combination of CdS with CdTe layers grown by high temperature growth methods such as closed space sublimation (CSS) or close spaced vapour transport (CSVT) for a long period. Depending on the growth technique, material growth mechanisms, micro-structure and impurity inclusions are going to vary. Although there are a large number of publications reporting material characterisation, deep understanding is required on material issues such as defects and doping concentrations.The next area needing deeper understanding is the postgrowth chemical and heat treatment. The devices fabricated using as-made CdTe materials show poor device performance in the range ~(0-6)% depending on the growth technique used. However, from 1976 [2], the researchers were aware of the drastic improvement of the device performance after heat treatment around 450 °C in air, in the presence of CdCl 2 . This was known as "CdCl 2 treatment" and device efficiencies improved to mid-teens achieving good solar cell performance. Although there were tremendous efforts to explore the complexity of changes during this treatment, full understanding has not yet been achieved.The third main area of complexity comes from the CdTe/electrical back contact formation. It is essential to clean the CdTe surface after CdCl 2 treatment, and researchers were using different chemicals to clean the surface prior to metallisation. Various electrical contacts have been used to complete the devices and varying results have been reported in the literature [3]. Initial high efficiency, reproducibility and yield, stability and lifetime are main features of fully fabricated devices to establish. Some of these Abstract Thin film solar cells based on CdS/CdTe hetero-structure has shown a drastic improvement changing from 16.5 to 22.1% efficiency during a short period of time from ~2013 to ~2016. This has happened in the industrial environment and the open research in this field has stagnated over a period of two decades prior to ~2013. Most of the issues of this hetero-structure were not clear to the photovoltaic (PV) community and research efforts should be directed to unravel its complex nature. Issues related to materials, post-growth treatment, chemical etching prior to metallisation and associated device physics are the main areas needing deeper understanding in order to further develop this device. After a comprehensive research programme in both academia and in industry on these materials, surfaces and interfaces and fully fabricated devices over a period of over three decades by the main author, the current knowledge as understood today, on all above mentioned complex issues are presented in this paper. Full understanding of this structure will enable PV developers to further improve the ...

Electroplating of Semiconductor Materials for Applications in Large Area Electronics: A Review

“…With the effective purification of the electrolyte, intrinsic doping has been demonstrated in the literature for binary [38,67], ternary [68], and quaternary [69,70] semiconductor materials by changing the deposition voltage. Taking an example of a I-III-VI 2 semiconductor materials such as CuInGaSe 2 , the stoichiometric semiconductor layer consists of 25% of the group I element, 25% of the group III elements, and 50% of group VI element.…”

Magnesium Incorporation in n-CdTe to Produce Wide Bandgap p-Type CdTe:Mg Window Layers

“…Hence, the co-deposition of cadmium and tellurium begins hereafter and Te-rich CdTe starts to deposit from ~900 mV onward. As higher cathodic voltage is applied, Cd starts increasingly incorporating to the layer and eventually Cd-rich CdTe deposits [13]. Then, a rise of current density at ~1250 mV (point B in Figure 1) indicates the inclusion of Mg having an E o of −2.372 V (with reference to standard H2 electrode), to the deposited CdTe layer according to the electrochemical reaction Equation 3:…”

“…This voltage difference is commonly referred as the PEC signal. The setup in this work is calibrated using a glass/FTO/CdS sample beforehand, since the conduction type of CdS is always known to be n-type [13]. For n-type layers the PEC signal is negative and for p-type it is positive for the setup used in this work, whereas for metals, insulators and intrinsic semiconductors PEC signal is ideally zero.…”

“…Voltammetric studies have indicated the possibility of Mg inclusion in the Cd-rich CdTe layer at 1400 mV. Cd richness in the CdTe layer produces a n-type material that is likely to ensure lesser defects than that of its Te-rich p-type counterpart due to less Te precipitation [4,13,16]. Therefore, the growth voltage has been kept constant at 1400 mV.…”

Synthesis of cadmium telluride epitaxial films on Al2O3 substrates and their electrophysical properties

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