Universality of mobility-gate field characteristics of electrons in the inversion charge layer and its application in MOSFET modeling

Lee, S.-W.

doi:10.1109/43.31529

Cited by 19 publications

(2 citation statements)

References 17 publications

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“…Here µ 0 is the low field mobility dependent on the channel surface concentration (N s ) [22], θ is the mobility degradation coefficient given by α θ C ox /(2ε 0 ε si ), α θ is the scattering constant (1.35 × 10 −6 cm V −1 [23]) and θ b is assigned a small value (0.005 V −1 ) typical of n-channel devices.…”

Section: Intrinsic Capacitancementioning

confidence: 99%

Parasitic capacitance characteristics of deep submicrometre grooved gate MOSFETs

Sreelal

Lau²,

Samudra

2002

Semicond. Sci. Technol.

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Grooved gate metal-oxide-semiconductor field-effect transistors (MOSFETs) are known to alleviate many of the short channel and hot carrier effects that arise when MOSFET devices are scaled down to very short channel lengths. However, they exhibit much higher parasitic capacitance with stronger bias dependence when compared to conventional planar devices. In this paper, we present a model for gate-to-drain and gate-to-source capacitance characteristics of a deep submicrometre grooved gate MOSFET. Both the intrinsic and extrinsic parts of the capacitance are modelled separately. In particular, the model presents a novel but simple way to account for the accumulation layer formation in the source/drain region of MOSFETs due to the application of the gate voltage. The results are compared with those obtained from a two-dimensional device simulator. The close match between the modelled and simulated data establishes the validity of the model. The model is then used to account for the superiority of capacitance characteristics of planar device structures and to arrive at optimization guidelines for grooved gate devices to match these characteristics.

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Section: Intrinsic Capacitancementioning

confidence: 99%

Parasitic capacitance characteristics of deep submicrometre grooved gate MOSFETs

Sreelal

Lau²,

Samudra

2002

Semicond. Sci. Technol.

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show abstract

“…For example, to a first-order approximation, the threshold voltage decreases linearly as transistor length decreases and increases as transistor width decreases [11]. Trends in other parameters such as mobility are also observed [12], [13]. Advanced transistor models [14]- [17] attempt to address small-geometry effects and can be used for accurate simulation of near submicron transistors.…”

Section: Introductionmentioning

confidence: 99%

Explicit geometry dependence of MOS transistor parameters by the pseudoboundary method

Gowda

Sheu

1992

Analog Integr Circ Sig Process

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The pseudoboundary method is an engineering technique to extend the use of a single parameter set over the entire geometric design space for VLSI circuits. The technique eliminates adverse effects, such as negative output conductance, by clamping the evaluation of geometric dependence terms at the systematically determined boundaries of a primary region. The use of this technique is essential for accurate simulation of analog and digital circuits as well as prediction of circuit performance using next-generation submicron VLSI fabrication technologies. Results demonstrating the effectiveness of the technique using the widely accepted Berkeley short-channel IGFET model (BSIM) are presented, with data from transistors of different geometries ranging from 0.5 to 70/zm.

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Extraction of MOSFET carrier mobility characteristics and calibration of a mobility model for numerical device simulation

Lee

1990

Solid-State Electronics

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Universality of mobility-gate field characteristics of electrons in the inversion charge layer and its application in MOSFET modeling

Cited by 19 publications

References 17 publications

Parasitic capacitance characteristics of deep submicrometre grooved gate MOSFETs

Parasitic capacitance characteristics of deep submicrometre grooved gate MOSFETs

Explicit geometry dependence of MOS transistor parameters by the pseudoboundary method

Extraction of MOSFET carrier mobility characteristics and calibration of a mobility model for numerical device simulation

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