Universal impurity ionization parameters in MIS C-V freeze-out characteristics and direct extraction of surface doping concentration

This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, bandgap widening, and uniformly distributed traps in the bandgap do not change the qualitative behavior of the threshold voltage over temperature. Care should be taken because dopant freezeout results in a different physical definition of the threshold voltage. Using different definitions changes significantly the threshold current level. The proposed model is experimentally validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process down to 4.2 K. Our modeling results suggest that a pMOSspecific phenomenon in the gate stack is responsible for the non-saturating temperature behavior of the threshold voltage in pMOS devices.

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Universal impurity ionization parameters in MIS C-V freeze-out characteristics and direct extraction of surface doping concentration

Cited by 4 publications

References 11 publications

Analysis of the relationship between the kink effect and the indium levels in MOS transistors

Analysis of the relationship between the kink effect and the indium levels in MOS transistors

Novel low-temperature C-V technique for MOS doping profile determination near the Si/SiO/sub 2/ interface

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

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