Novel low-temperature C-V technique for MOS doping profile determination near the Si/SiO/sub 2/ interface

Pirovano, A.; Lacaita, A.L.; Pacelli, A.; Benvenuti, A.

doi:10.1109/16.915719

Cited by 7 publications

(4 citation statements)

References 17 publications

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“…This was previously attributed to the field-assisted ionization of frozen-out dopants in the channel [13]. However, this ionization process should already be completed before threshold is reached as evidenced by low-temperature C-V plots [16]- [20]. Instead, interface traps close to the band edge are known to be important at cryogenic temperature [21], [22].…”

Section: Introductionmentioning

confidence: 99%

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Beckers

Jazaeri

Grill

et al. 2020

IEEE J. Electron Devices Soc.

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This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, bandgap widening, and uniformly distributed traps in the bandgap do not change the qualitative behavior of the threshold voltage over temperature. Care should be taken because dopant freezeout results in a different physical definition of the threshold voltage. Using different definitions changes significantly the threshold current level. The proposed model is experimentally validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process down to 4.2 K. Our modeling results suggest that a pMOSspecific phenomenon in the gate stack is responsible for the non-saturating temperature behavior of the threshold voltage in pMOS devices.

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Section: Introductionmentioning

confidence: 99%

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Beckers

Jazaeri

Grill

et al. 2020

IEEE J. Electron Devices Soc.

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“…With measurements at 77 K, the nonuniform V FB shift is evidence of quantization. Two additional cryogenic-temperature effects, the kink effect, caused by dopant freeze-out,34 and deep depletion, caused by minimal thermal generation of minority carriers, are also observed. This will be further investigated later.…”

mentioning

confidence: 94%

Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications

Lee

Meteer

Venkatasubramanian

et al. 2005

Journal of Elec Materi

195

148

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The self-assembly of metal nanocrystals including Au, Ag, and Pt on ultrathin oxide for nonvolatile memory applications are investigated. The self-assembly of nanocrystals consists of metal evaporation and selective rapid-thermal annealing (RTA). By controlling process parameters, such as the thickness of the deposited film, the post-deposition annealing temperatures, and the substrate doping concentration, metal nanocrystals with density of 2-4 ϫ 10 11 cm Ϫ2 , diameter less than 8.1 nm, and diameter deviation less than 1.7 nm can be obtained. Observation by scanning-transmission electron microscopy (STEM) and convergent-beam electron diffraction (CBED) shows that nanocrystals embedded in the oxide are nearly spherical and crystalline. Metal contamination of the Si/SiO 2 interface is negligible, as monitored by STEM, energy dispersive x-ray spectroscopy (EDX), and capacitance-voltage (C-V) measurements. The electrical characteristics of metal, nanocrystal nonvolatile memories also show advantages over semiconductor counterparts. Large memory windows shown by metal nanocrystal devices in C-V measurements demonstrate that the work functions of metal nanocrystals are related to the charge-storage capacity and retention time because of the deeper potential well in comparison with Si nanocrystals.

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“…For example, a formula to extract the doping profile of metal-oxide-semiconductor (MOS) devices from their capacitance-voltage (C-V ) characteristics was derived in Ref. [9]. Some formulas derived from the current-voltage relationship of Schottky diodes have been exploited to calculate their saturation current and barrier height.…”

Section: Introductionmentioning

confidence: 99%

A novel physical parameter extraction approach for Schottky diodes

Wang¹,

Chen²,

Xu³

2015

Chinese Phys. B

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Parameter extraction is an important step for circuit simulation methods that are based on physical models of semiconductor devices. A novel physical parameter extraction approach for Schottky diodes is proposed in this paper. By employing a set of analytical formulas, this approach extracts all of the necessary physical parameters of the diode chip in a unique way. It then extracts the package parasitic parameters with a curve-fitting method. To validate the proposed approach, a model HSMS-282c commercial Schottky diode is taken as an example. Its physical parameters are extracted and used to simulate the diode's electrical characteristics. The simulated results based on the extracted parameters are compared with the measurements and a good agreement is obtained, which verifies the feasibility and accuracy of the proposed approach.

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Novel low-temperature C-V technique for MOS doping profile determination near the Si/SiO/sub 2/ interface

Cited by 7 publications

References 17 publications

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications

A novel physical parameter extraction approach for Schottky diodes

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