Understanding the Impact of Annealing on Interface and Border Traps in the Cr/HfO₂/Al₂O₃/MoS₂ System

Abstract

Top-gated, few-layer MoS 2 transistors with HfO 2 (6 nm)/Al 2 O 3 (3 nm) gate dielectric stacks are fabricated and electrically characterized by capacitance−voltage (C−V) measurements to study electrically active traps (D it ) in the vicinity of the Al 2 O 3 /MoS 2 interface. Devices with low D it and high D it are both observed in C−V characterization, and the impact of H 2 / N 2 forming gas annealing at 300 and 400 °C on the D it density and distribution is studied. A 300 °C anneal is able to reduce the D it significantly, while the 400 °C anneal increases defects in the gate stack. Simulation with modeled defects suggests a sizable decrease in D it , half the amount of positive fixed charge in the dielectric, and slightly increased unintentional doping in MoS 2 after a 300 °C anneal. In the as-fabricated devices displaying high D it levels, the energy distribution of the D it located at the Al 2 O 3 /MoS 2 interface is continuous from the conduction band edge of MoS 2 down to 0.13−0.35 eV below the conduction band edge. A plausible D it origin in our experiments could come from the unexpected oxygen atoms that fill the sulfur vacancies during the UV−O 3 functionalization treatment. The border trap concentration in Al 2 O 3 is the same, both before and after the anneal, suggesting a different origin of the border traps, possibly due to the low-temperature atomic-layer-deposited process. KEYWORDS: molybdenum disulfide (MoS 2 ), high-k dielectrics, Al 2 O 3 , interface traps, border traps, capacitance−voltage (C−V)

Few-Layered MoS2 Field-Effect Transistors with a Vertical Channel of Sub-10 nm

“…The interface-state density ( D it ) between the MoS 2 channel and the HfO 2 gate dielectric can be extracted using eqs and . where k is the Boltzmann’s constant, T is the environmental temperature (300 K), q is the electron charge, C it is the interface-state capacitance per unit area, ε 0 is the vacuum permittivity, and ε is the relative permittivity of the HfO 2 gate dielectric. With ε = 19, t ox = 10 nm (thickness of HfO 2 ), and SS = 73 mV/dec, D it can be calculated as 2.28 × 10 12 cm –2 eV –1 , which is consistent with the previous results of the MoS 2 /HfO 2 interface, , but considerably smaller than ∼10 13 cm –2 eV –1 of the transistor without annealing, indicating that forming gas annealing can significantly improve interface quality …”

“…With ε = 19, 31 t ox = 10 nm (thickness of HfO 2 ), and SS = 73 mV/dec, D it can be calculated as 2.28 × 10 12 cm −2 eV −1 , which is consistent with the previous results of the MoS 2 /HfO 2 interface, 9,31 but considerably smaller than ∼10 13 cm −2 eV −1 of the transistor without annealing, indicating that forming gas annealing can significantly improve interface quality. 32 Field-effect mobility can be extracted from the I DS −V GS curves in the linear region at V DS = 0.1 V by using the following equation…”

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS

“…Although the picture is far to be clear, it is believed that sulfur vacancies in MoS 2 layers are a major source of instability [15], [16]. These defects introduce interfacial bandgap states with a D it peak of the order of 10 12 ÷ 10 13 cm −2 eV −1 regardless of the gate dielectrics [16], [19], [33], [34], [35], [36]. Some work [34], [37] reported that sulfur vacancies introduce localized donor states around 0.35 eV from the midgap.…”

“…Defects are responsible for additional variability of the transport characteristics and for reliability issues, such as hysteresis and bias temperature instability. In particular, hysteresis can increase the measured memory window in FG memories and has been attributed to both intrinsic traps in the channel material (such as sulfur vacancies in MoS 2 [15], [16]) and/or to slower dielectric traps [17], [18], [19]. In addition, geometry and process have a large impact on device characteristics.…”

Performance‐Enhanced CsPbBr3/HfO2/Si Heterostructure Optoelectronics through the Tunneling Effect

“…HfO 2 is a material with high permittivity (≈25) and a large bandgap (5.4 eV), [ 29,30 ] and it exhibits a high breakdown voltage, a low leakage current, and excellent stability. It is deemed to be the most promising gate insulator for replacing SiO 2 in field‐effect transistors (FETs), [ 31,32 ] and it has been applied to fabricate high‐performance electronic devices such as resistive random access memory (RRAM) and capacitors. [ 33–36 ] Additionally, HfO 2 can be used as a refractory material in gate insulation because of its high melting point (2758 °C).…”