Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS

Abstract

Two-dimensional materials (2DMs) have found potential applications in many areas of electronics, such as sensing, memory systems, optoelectronics, and power. Despite an intense experimental work, the literature is lacking of accurate modeling of nonvolatile memories (NVMs) based on 2DMs. In this work, using technology CAD simulations and model calibration with experiments, we show that the experimental program/erase characteristics of floating-gate (FG) memory devices based on monolayer molybdenum disulphide can be explained by considering bandgap trap states at the dielectricsemiconductor interface. The simulation model includes a classical approach based on drift-diffusion longitudinal channel transport and on nonlocal Wentzel-Kramers-Brillouin (WKB) tunneling for transversal transport (responsible of FG charging/discharging) and for tunneling at contacts. From hysteresis and pulse programming simulations on scaled devices, we find that the long-channel programming window is still maintained at∼100 nm and that process improvements aimed at reducing the concentration of interface traps in the semiconducting bandgap could significantly optimize memory operation.

Simultaneously ultrafast and robust two-dimensional flash memory devices based on phase-engineered edge contacts

“…With their atomically flat layer structure, the emerging two-dimensional van der Waals (2D vdW) materials have numerous ways to engineer an ideal Schottky barrier, including using phase-engineered or vdW contact 16 , 17 . They could also be integrated at high packing density yet with low defect density and clean interfaces 18 , 19 , which are desirable for ultrafast and robust memory operation by providing an ideal charge injection interface and durable tunneling layer 20 . However, the performance of 2D flash memory in previous literatures falls behind of the expectation in spite of various channel and float gate used 21 – 27 .…”

Simultaneously Ultrafast and Super-Robust Two-dimensional Flash Memory Enabled by Phase Engineered Edge Contact

“…16,17 They could also be integrated at high packing density yet with low defect density and clean interfaces, 18,19 which are desirable for ultrafast and robust memory operation by providing an ideal charge injection interface and durable tunneling layer. 20 However, the performance of 2D flash memory in previous literatures falls behind of the expectation in spite of various channel and float gate used. [21][22][23][24][25][26][27] Until recently, 20-160 ns superior operation speed was achieved in InSe and MoS2 flash memories based on the clean interface in vdW heterostructures or hot carrier injection directly though the ultrathin 2D material.…”