Few-Layered MoS₂ Field-Effect Transistors with a Vertical Channel of Sub-10 nm

Abstract

Few-layered molybdenum disulfide (MoS2) has demonstrated promising advantages for the integration of next-generation electronic devices. A vertical short-channel MoS2 transistor with a channel length of sub-10 nm can be realized using mica as the insulated mesa and MoS2 flake dry-transferred onto the mica as the channel. A near-perfect symmetrical and fully saturated output characteristic can be obtained for the positive or negative drain–source voltage. This result is attributed to an effective transformation of the drain–source electrode contact from Schottky contact to Ohmic contact via forming gas annealing. The vertical-channel MoS2 transistor with a channel length of 8.7 nm exhibits excellent electrical characteristics, for example, a negligible hysteresis voltage of 60 mV, an extraordinarily small subthreshold swing of 73 mV/dec, a considerably weakened drain-induced barrier-lowering effect (100 mV/V), and the first-reported intrinsic delay time of 2.85 ps. Moreover, a logic inverter can be realized using the two vertical-channel MoS2 transistors, with a high voltage gain of 33. Experimental results indicate that the developed method is a potential approach for fabricating MoS2 transistors with an ultrashort channel and high performance, and consequently, manufacturing MoS2-based integrated circuits.

Vertical MoS2 transistors with sub-1-nm gate lengths

“…The iterative progresses of gate length as a function of time line is shown in Fig. 4f 14,[21][22][23][24][25][26][27][28][29][30][31][32][33] . From 2D planar device to 3D FinFET and further GAAFET, the structure of Si transistors gradually changes with better gate control ability.…”

Perspectives of 2D Materials for Optoelectronic Integration

“…[250] A MoS 2 FET with sub-10 nm channel length was demonstrated, which exhibits high on/off current ratio (≈10 6 -10 7 ) and no obvious short-channel effects. [251][252][253][254][255][256] A 2D transistor with a 1 nm physical gate was constructed with a MoS 2 bilayer channel and a single-walled carbon nanotube as the gate electrode, signifying the potential of TMDCs to solve the problems of silicon transistors scaling in the future. [257] The demonstration of n-and p-type transistors on the same substrate is needed to enable low-power logic circuits.…”

2D Layered Material Alloys: Synthesis and Application in Electronic and Optoelectronic Devices

“…That is, normally only one type of charge polarity tends to be formed for a specific S2DLM. For example, MoS 2 is a natively n‐type semiconductor, presumably because of the omnipresent electron‐donating sulfur vacancies, [ 178 ] while WSe 2 is a natively p‐type semiconductor. [ 179 ] As the composition of 2DLM alloys can be markedly tuned over a wide range by virtue of the high miscibility of the host materials with a general stoichiometric formula and analogous crystal structure, it is plausible that the native propensity of electric transport characteristics of 2DLMs can be significantly modulated through alloy engineering.…”