Understanding Reduced-Voltage Operation in Modern DRAM Devices

Chang, Ki-Ho; Yağlıkçı, A. Giray; Ghose, Saugata; Agrawal, Aditya; Chatterjee, Niladrish; Kashyap, Abhijith; Lee, Donghyuk; O'Connor, Mike; Hassan, Hasan; Mutlu, Onur

doi:10.1145/3078505.3078590

Cited by 85 publications

(20 citation statements)

References 114 publications

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“…First, many works [16,22,52,59,74,77,78,82,106,109,110] show that the average DRAM access latency can be shortened by reducing DRAM access timings for particular memory locations that can tolerate faster accesses. This can be done safely because, although DRAM standards call for constant access timings across all memory locations, the minimum viable access timings that the hardware can support actually differ across memory locations due to factors such as heterogeneity in the circuit design [17,78] and manufacturing process variation in circuit components [16,22,52,74,263].…”

Section: Solutions To Reduce the Dram Access Latencymentioning

confidence: 99%

“…To identify new access timings, the majority of prior works [13,16,17,22,52,55,73,75,91,171,263,[271][272][273] perform extensive experimental characterization studies across many (e.g., hundreds or thousands of) DRAM chips. These studies account for three primary sources of variation that affect the access timings of a given memory location.…”

Section: Application To Today's Commodity Dram Chipsmentioning

confidence: 99%

“…Examples of measured quantities include: aggregate error rates, per-cell probabilities of error, and spatial/temporal error distributions. These measurements can be made using testing infrastructures ranging from industry-standard largescale testing equipment [353,354] to home-grown tools based on commodity FPGAs [16,29,55,65,90,171,263,272,[355][356][357][358] or DRAM-based computing systems [236,262,273,359,360].…”

Section: Information Flow During Testingmentioning

confidence: 99%

See 2 more Smart Citations

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns.To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

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Section: Solutions To Reduce the Dram Access Latencymentioning

confidence: 99%

Section: Application To Today's Commodity Dram Chipsmentioning

confidence: 99%

Section: Information Flow During Testingmentioning

confidence: 99%

See 1 more Smart Citation

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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show abstract

“…After programming, the capacitors with the charge Q store 1s, and the ones with the charge "0" store 0s. Due to the constant leakage of these charges, they are compared during read cycles with the charge left on a reference cell that was initially charged with Q/2 [36,37]. Approximately every million cycles, the DRAM is refreshed.…”

Section: Microelectronics For Ternary Computersmentioning

confidence: 99%

Can Ternary Computing Improve Information Assurance?

et al. 2018

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Abstract:Modern computer microarchitectures build on well-established foundations that have encouraged a pattern of computational homogeneity that many cyberattacks depend on. We suggest that balanced ternary logic can be valuable to Internet of Things (IoT) security, authentication of connected vehicles, as well as hardware and software assurance, and have developed a ternary encryption scheme between a computer and smartcard based on public key exchange through non-secure communication channels to demonstrate the value of balanced ternary systems. The concurrent generation of private keys by the computer and the smartcard uses ternary schemes and cryptographic primitives such as ternary physical unclonable functions. While general purpose ternary computers have not succeeded in general use, heterogeneous computing systems with small ternary computing units dedicated to cryptographic functions have the potential to improve information assurance, and may also be designed to execute binary legacy codes.

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“…The SRAM based PUFs are not particularly immune to side channel attacks. Significant research efforts have been published regarding the design of PUFs with Flash RAMs [39][40], DRAMs [41][42][43][44], magnetic RAMs [45][46], and resistive RAMs [47][48][49]]. The cryptographic protocols leveraging memory PUFs are in general distinct from the ones developed with other mainstream PUFs such as ring oscillators, or gate delay arbiters.…”

Section: Memory Based Pufsmentioning

confidence: 99%

Design of True Random Numbers Generators with Ternary Physical Unclonable Functions

Cambou¹

2018

Adv. sci. technol. eng. syst. j.

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Memory based ternary physical unclonable functions contain cells with fuzzy states that are exploited to create multiple sources of physical randomness, and design true random numbers generators. A XOR compiler enhances the randomness of the binary data streams generated with such components, while a modulo-3 addition enhances the randomness of the native ternary data streams, also generated with the same method. Deviations from perfect randomness of these random numbers, in terms of probability to be non-random, was reported as low as 10-10 in the experimental section of this paper, which is considered as extremely random based on NIST criteria.

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Understanding Reduced-Voltage Operation in Modern DRAM Devices

Cited by 85 publications

References 114 publications

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Can Ternary Computing Improve Information Assurance?

Design of True Random Numbers Generators with Ternary Physical Unclonable Functions

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