Understanding charge traps for optimizing Si-passivated Ge nMOSFETs

Abstract

Background and key advance: Ge is an attractive channel material offering high hole and electron mobility, and therefore of interest for future p-and n-FET technologies. Ge nFETs can be made through two routes: GeO2/high-k directly on Ge [1] or using a Si-passivated monolayer (ML) [2]. The former offers higher mobility but poor reliability [3] , while the Si-passivated option has a better balance between mobility and reliability, making it promising for the debut of Ge CMOS [4]. However, significant trapping-induced PBTI compared with the Si counterpart is the key hurdle for its practical use. To optimize it, there is a pressing need for understanding the properties of these traps as well as their impact on time-dependent mobility and reliability. In this work, for the first time, two types of electron traps are unambiguously identified in Ge nFETs, which are controlled respectively by a) the HK layer thickness and b) the growth conditions used for the Si-passivated layer. These different traps exhibit different impacts on mobility degradation. Based on this, process is improved, as experimentally verified with maximum operation overdrive enhanced by a factor of ~1.7 (4&6ML). Device fabrication: Si-passivated Ge nFETs were fabricated using a replacement metal gate high-k last process with the gate stack shown in Fig.1. After dummy gate removal and pre-cleaning, the thin Si layer was epitaxially grown on the Ge channel with either Si3H8/350 o C or SiH4/500 o C. Laser annealing was performed at 750 o C. Other process differences are detailed in Table 1. Based on the process conditions, the devices are split into groups: D1&D2 each with 4&6 Si-ML were used to understand the traps, their origin and dependence on processing conditions. Based on this understanding, the process was designed to fabricate D3, verifying the expected improvement. All measurements are with a speed of 5μs. Two types of traps: Oxide traps are investigated using the energy profiling technique [5] (Fig.2a). When charging bias, Vgch, is low, the profiles extracted from discharging after filling at different Vgch overlap well (Fig.3a). However, for higher Vgch, they deviate from each other (Fig.3b). This deviation is not due to the incomplete discharging (Fig.2b). Therefore, Figs.3a&b indicate that there exist two types of electron traps in the dielectric with different filling mechanisms: Type-A capture electrons without changing their energy levels (inset of Fig.3a); Type-B, after capturing electrons, shift energy levels down from ground level to charged level (inset of Fig.3b), resulting in the increased ΔVth under same surface potential after filling at higher Vgch (Fig.3b). Following procedure proposed in ref 5 (Fig.4a), Type-A are separated and given in Fig.4b and Type-B can be obtained by subtracting Type-A from total (Fig.4b) and given in Fig.4c. To compare the energy profile for different processes and MLs in the next section, ΔVth~(Vg-ΔVth) is converted to ΔNot~(Ef-Ec_SiO2) (Fig.5) [5]. Type-A are both within Si bandgap and above Ec_Si, ...

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