Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices

Patel, Minesh; Kim, Jeremie S.; Hassan, Hasan; Mutlu, Onur

doi:10.1109/dsn.2019.00017

Cited by 48 publications

(82 citation statements)

References 96 publications

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“…What sets DRAM disturbance errors apart from other technologies' disturbance errors is that 1) DRAM is exposed to the user-level programs and manipulated directly by a program's load and store instructions (which we do not anticipate to change any time soon, since direct data manipulation in main memory is a fundamental component of programming languages and systems), and 2) in modern DRAM, as opposed to other technologies, strong error correction mechanisms are not commonly employed (either in the memory controller or the memory chip). The success of DRAM scaling until recently has not relied on a memory controller that corrects errors (other than performing periodic refresh and more recently employing very simple single-error correcting codes [9,113,185,186,191,195]). Instead, DRAM chips were implicitly assumed to be error-free and did not require the help of the controller to operate correctly.…”

Section: H Rowhammer In a Broader Contextmentioning

confidence: 99%

RowHammer: A Retrospective

Mutlu

Kim

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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157

129

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This retrospective paper describes the RowHammer problem in Dynamic Random Access Memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 conference [133]. RowHammer is a prime (and perhaps the first) example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability. It is the phenomenon that repeatedly accessing a row in a modern DRAM chip causes bit flips in physically-adjacent rows at consistently predictable bit locations. RowHammer is caused by a hardware failure mechanism called DRAM disturbance errors, which is a manifestation of circuit-level cell-to-cell interference in a scaled memory technology.Researchers from Google Project Zero demonstrated in 2015 that this hardware failure mechanism can be effectively exploited by user-level programs to gain kernel privileges on real systems. Many other follow-up works demonstrated other practical attacks exploiting RowHammer. In this article, we comprehensively survey the scientific literature on RowHammer-based attacks as well as mitigation techniques to prevent RowHammer. We also discuss what other related vulnerabilities may be lurking in DRAM and other types of memories, e.g., NAND flash memory or Phase Change Memory, that can potentially threaten the foundations of secure systems, as the memory technologies scale to higher densities. We conclude by describing and advocating a principled approach to memory reliability and security research that can enable us to better anticipate and prevent such vulnerabilities.

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Section: H Rowhammer In a Broader Contextmentioning

confidence: 99%

RowHammer: A Retrospective

Mutlu

Kim

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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157

129

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“…As there is a large number of rows in the chip, the memory controller issues a refresh command once every 7.8 us to complete the refresh cycle for the entire DRAM in 64 ms. A single refresh command typically refreshes multiple rows in a batch in hundreds of nanoseconds. 2 DRAM refresh consumes a significant amount of energy and its overhead is expected to further increase in future DRAM devices as DRAM capacity increases [3,9,13,24,46,48,49,51,72,73,81,83,87,[92][93][94]114]. For example, Liu et al [72] show that refreshes constitute 15% of the total DRAM energy for a 4Gb DDR3 chip, and the fraction of DRAM energy spent on DRAM refresh is projected to increase as DRAM chips become denser (e.g., refreshes would consume about 50% of the total DRAM energy in future 64 Gb DRAM chips).…”

Section: Dram Organization and Operationmentioning

confidence: 99%

“…Refresh is a growing major energy and performance bottleneck with the scaling of the DRAM technology [46,72]. RTC mitigates this negative scaling trend [3,9,13,24,46,48,49,51,72,73,81,83,87,[92][93][94]114] for a class of applications by minimizing the need to refresh with its RTT and PAAR techniques. For a 64 Gb DRAM chip, even when working at peak bandwidth, refresh is expected to consume 46% of the total DRAM energy [45,72].…”

Section: Scalability Benefitsmentioning

confidence: 99%

Refresh Triggered Computation

Jafri

Hassan

Hemani

et al. 2020

ACM Trans. Archit. Code Optim.

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To employ a Convolutional Neural Network (CNN) in an energy-constrained embedded system, it is critical for the CNN implementation to be highly energy efficient. Many recent studies propose CNN accelerator architectures with custom computation units that try to improve the energy efficiency and performance of CNNs by minimizing data transfers from DRAM-based main memory. However, in these architectures, DRAM is still responsible for half of the overall energy consumption of the system, on average. A key factor of the high energy consumption of DRAM is the refresh overhead , which is estimated to consume 40% of the total DRAM energy. In this article, we propose a new mechanism, Refresh Triggered Computation (RTC) , that exploits the memory access patterns of CNN applications to reduce the number of refresh operations . RTC uses two major techniques to mitigate the refresh overhead. First, Refresh Triggered Transfer (RTT) is based on our new observation that a CNN application accesses a large portion of the DRAM in a predictable and recurring manner. Thus, the read/write accesses of the application inherently refresh the DRAM, and therefore a significant fraction of refresh operations can be skipped. Second, Partial Array Auto-Refresh (PAAR) eliminates the refresh operations to DRAM regions that do not store any data. We propose three RTC designs (min-RTC, mid-RTC, and full-RTC), each of which requires a different level of aggressiveness in terms of customization to the DRAM subsystem. All of our designs have small overhead. Even the most aggressive RTC design (i.e., full-RTC) imposes an area overhead of only 0.18% in a 16 Gb DRAM chip and can have less overhead for denser chips. Our experimental evaluation on six well-known CNNs shows that RTC reduces average DRAM energy consumption by 24.4% and 61.3% for the least aggressive and the most aggressive RTC implementations, respectively. Besides CNNs, we also evaluate our RTC mechanism on three workloads from other domains. We show that RTC saves 31.9% and 16.9% DRAM energy for Face Recognition and Bayesian Confidence Propagation Neural Network (BCPNN) , respectively. We believe RTC can be applied to other applications whose memory access patterns remain predictable for a sufficiently long time.

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“…Model Selection. EDEN applies a maximum likelihood estimation (MLE) [128] procedure to determine 1) the parameters (P, F A , P B , F B , P W , F W , F V 1 and F V 0 ) of each error model, and 2) the error model that is most likely to produce the errors observed in the real approximate DRAM chip. In case two models have very similar probability of producing the observed errors, our selection mechanism chooses Error Model 0 if possible, or one of the error models randomly otherwise.…”

Section: Enabling Eden With Error Modelsmentioning

confidence: 99%

Eden

Koppula

Orosa

Yağlıkçı

et al. 2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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The effectiveness of deep neural networks (DNN) in vision, speech, and language processing has prompted a tremendous demand for energy-efficient high-performance DNN inference systems. Due to the increasing memory intensity of most DNN workloads, main memory can dominate the system's energy consumption and stall time. One effective way to reduce the energy consumption and increase the performance of DNN inference systems is by using approximate memory, which operates with reduced supply voltage and reduced access latency parameters that violate standard specifications. Using approximate memory reduces reliability, leading to higher bit error rates. Fortunately, neural networks have an intrinsic capacity to tolerate increased bit errors. This can enable energy-efficient and high-performance neural network inference using approximate DRAM devices.Based on this observation, we propose EDEN, the first general framework that reduces DNN energy consumption and DNN evaluation latency by using approximate DRAM devices, while strictly meeting a user-specified target DNN accuracy. EDEN relies on two key ideas: 1) retraining the DNN for a target approximate DRAM device to increase the DNN's error tolerance, and 2) efficient mapping of the error tolerance of each individual DNN data type to a corresponding approximate DRAM partition in a way that meets the user-specified DNN accuracy requirements.We evaluate EDEN on multi-core CPUs, GPUs, and DNN accelerators with error models obtained from real approximate DRAM devices. We show that EDEN's DNN retraining technique reliably improves the error resiliency of the DNN by an order of magnitude. For a target accuracy within 1% of the original DNN, our results show that EDEN enables 1) an average DRAM energy reduction of 21%, 37%, 31%, and 32% in CPU, GPU, and two different DNN accelerator architectures, respectively, across a variety of state-ofthe-art networks, and 2) an average (maximum) speedup of 8% (17%) and 2.7% (5.5%) in CPU and GPU architectures, respectively, when evaluating latency-bound neural networks.

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Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices

Cited by 48 publications

References 96 publications

RowHammer: A Retrospective

RowHammer: A Retrospective

Refresh Triggered Computation

Eden

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