Understanding and minimizing ground bounce during mode transition of power gating structures

Kim, Suhwan; Kosonocky, Stephen; Knebel, D.R.

doi:10.1145/871510.871515

Cited by 23 publications

(36 citation statements)

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“…Moreover, it gives the designer the freedom to set the maximum tolerable noise according to the design's own noise margins, thus controlling the compromise between wakeup latency and peak noise. Our results show an average of 44% improvement in peak noise over SPD while maintaining similarly low settling times, and compared to Uniformly Gradual Power Gating [4], the settling time is around 78% lower while the peak fluctuation is also improved by 14%. The algorithm was simulated on seven ISCAS85 benchmark circuits of varying sizes.…”

Section: Introductionmentioning

confidence: 65%

“…This model factors in the inductance of the PDN, and produces an underdamped response in the power and ground lines. Seven ISCAS85 [9] benchmark circuits of various sizes have been simulated using the proposed CEMS-PG as well as three other techniques: Non-Throttled (NT) Power Gating (the nonoptimized brute force approach), Uniformly Gradual (UG) Power Gating [4] which increases the sleep transistor effective capacity in a uniform way, and Staggered-Phase Damping (SPD) [7]. The constraints of CEMS-PG were set to a peak noise amplitude of 150mV and a maximum current standard variation of 0.2mA.…”

Section: Implementation and Resultsmentioning

confidence: 99%

“…Another technique connects the circuit block to separate bypass power lines [5], which requires a duplication of the sleep device and power lines. It's also been proposed to divide the large sleep transistor into multiple smaller devices in parallel, switching them on gradually [4], while another technique uses dynamic programming to find the best wake-up schedule in a Distributed Sleep Transistor Network, consisting of the best wakeup sequence and delay gaps [6]. These approaches, however, do not create the actual partitioning and require that to be already provided.…”

Section: Related Workmentioning

confidence: 99%

“…Alternatively, most techniques achieve this through a progressive wakeup, either by turning on different parts of the circuit consecutively, or by gradually increasing the gate voltage of the sleep device [4,10]. The end result is an effective reduction in the inrush current, but at the cost of an increased wakeup time.…”

Section: Introductionmentioning

confidence: 99%

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CEMS-PG: A parametrized algorithm for balanced partitioning and wakeup of power gated circuits

Farah

Bayoumi

2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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Power gating can be a source of disturbances detrimental to IC robustness and response time. This work introduces Current-Equalized Multi-Stage Power Gating (CEMS-PG), a parameterized algorithm for finding an efficient wakeup approach given a maximum tolerable fluctuation in the power distribution network. Applying both partitioning and scheduling, CEMS-PG efficiently divides a power gated circuit into partitions with near-equal surge currents, making them suitable for an improved form of Staggered-Phase Damping. Our simulations show up to 44% improvement in wakeup time and 78% in peak noise, offering minimal compromise between the two.I.

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Section: Introductionmentioning

confidence: 65%

Section: Implementation and Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

CEMS-PG: A parametrized algorithm for balanced partitioning and wakeup of power gated circuits

Farah

Bayoumi

2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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“…For this reason, the first studies have focused on SSN due to IO buffers. In this context, specific design techniques have been proposed and developed that allow to significantly reduce the amount of power and ground bounce [5,6].…”

Section: Introductionmentioning

confidence: 99%

Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits

Azais¹,

Larguier²,

Renovell³

2007

16th Asian Test Symposium (ATS 2007)

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This paper analyzes the logic errors in digital circuits due to the presence of Simultaneous Switching Noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called 'Minimum Switch Condition' is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called 'Signal Coherence Condition' is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunction. DFT and ATPG recommendations are derived from this analysis.16th IEEE Asian Test Symposium

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Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits

Jiao

Kursun

2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Multi-threshold CMOS (MTCMOS) is the most widely used circuit technique for suppressing subthreshold leakage currents in idle circuits. When a conventional MTCMOS circuit transitions from SLEEP mode to ACTIVE mode, voltages of power and ground distribution networks are disturbed. Mode transition noise phenomenon in MTCMOS circuits is examined in this chapter. An MTCMOS circuit technique with three operating modes (tri-mode) is described for noise suppression during activation events. A threshold voltage tuning methodology is presented to further alleviate the mode transition noise with smaller sleep transistors in MTCMOS circuits. Alternative applications of tri-mode MTCMOS for data preservation and leakage power reduction in idle memory elements are also discussed.

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Understanding and minimizing ground bounce during mode transition of power gating structures

Cited by 23 publications

References 0 publications

CEMS-PG: A parametrized algorithm for balanced partitioning and wakeup of power gated circuits

CEMS-PG: A parametrized algorithm for balanced partitioning and wakeup of power gated circuits

Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits

Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits

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