Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits

Abstract

This paper analyzes the logic errors in digital circuits due to the presence of Simultaneous Switching Noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called 'Minimum Switch Condition' is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called 'Signal Coherence Condition' is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunction. DFT and ATPG recommendations are derived from this analysis.16th IEEE Asian Test Symposium

Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning

“…For a logic gate to perform its correct function (no metastability), the minimum difference between the circuit power supply and ground rails needs to be slightly higher than the largest magnitude of threshold voltage of the transistors in the gate [27], [28]. Since the following relation between the pMOS and nMOS transistor thresholds holds true,…”