UML-based multiprocessor SoC design framework

Abstract

This paper describes a complete design flow for multiprocessor systems-on-chips (SoCs) covering the design phases from system-level modeling to FPGA prototyping. The design of complex heterogeneous systems is enabled by raising the abstraction level and providing several system-level design automation tools. The system is modeled in a UML design environment following a new UML profile that specifies the practices for orthogonal application and architecture modeling. The design flow tools are governed in a single framework that combines the subtools into a seamless flow and visualizes the design process. Novel features also include an automated architecture exploration based on the system models in UML, as well as the automatic back and forward annotation of information in the design flow. The architecture exploration is based on the global optimization of systems that are composed of subsystems, which are then locally optimized for their particular purposes. As a result, the design flow produces an optimized component allocation, task mapping, and scheduling for the described application. In addition, it implements the entire system for FPGA prototyping board. As a case study, the design flow is utilized in the integration of state-of-the-art technology approaches, including a wireless terminal architecture, a network-on-chip, and multiprocessing utilizing RTOS in a SoC. In this study, a central part of a WLAN terminal is modeled, verified, optimized, and prototyped with the presented framework.

A system-level synthesis approach from formal application models to generic bus-based MPSoCs

“…PeaCE [14], on the other hand, supports automatic computation refinement while decision making mostly has to be performed manually. Daedalus [15], Koski [16], and SystemCoDesigner (SCD) [7] are system-level synthesis tools that automatically map applications to MPSoC targets. These tools support decision making and refinement for application computation, but decision making and refinement for communication is only supported for limited types of communication architectures.…”

Calibration of Abstract Performance Models for System-Level Design Space Exploration

“…As mentioned in our introduction, there are various related architectural exploration environments (e.g., [7,13,24,27,35]) that, like Sesame, also facilitate flexible system-level performance evaluation by providing support for mapping a behavioral application specification to an architecture specification. In Gries [18], an excellent survey is presented of various methods, tools and environments for early design space exploration.…”

A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications

“…However, the high degree of parallelism of processors makes programming of MPSoCs a challenging task. While many research groups have conducted research on optimally mapping an application onto a given MPSoC platform, e.g., Daedalus [19], SystemCoDesigner [9], Koski [13], System-on-Chip Environment (SCE) [1], etc., there is still only little work on defining the right programming model for MPSoCs.…”