Calibration of Abstract Performance Models for System-Level Design Space Exploration

Pimentel, Andy D.; Thompson, Mark; Polstra, Simon; Erbas, Cagkan

doi:10.1007/s11265-007-0085-2

Cited by 50 publications

(5 citation statements)

References 41 publications

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“…The open-source Sesame system-level MPSoC simulator [23] is deployed to evaluate mappings. The Sesame modeling and simulation environment facilitates efficient performance analysis of embedded (media) systems architectures.…”

Section: Experiments and Resultsmentioning

confidence: 99%

Run-time mapping algorithm for dynamic workloads using process merging transformations

Fatemi

Pimentel

2017

2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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Exploration of task mappings has an important role to achieve high performance in heterogeneous multi-processor system-on-chip (MPSoC) platforms. The application workloads in modern MPSoC-based embedded systems are becoming increasingly dynamic. Different applications concurrently execute and contend for resources in such systems. In this paper, a run-time algorithm is proposed to analytically evaluate the system throughput of to-be-executed applications (modelled as Kahn Process Networks, KPNs) in order to quickly determine a proper resource binding for these applications. Merging transformations on the KPNs are applied to capture the cases in which the number of processes in the KPN is larger than the number of available processing resources, thereby modeling the effects of binding multiple processes to a single processor. We evaluated our algorithm using a heterogeneous MPSoC system with several applications. Our experimental results revealed that during runtime, the performance of selected mapping with regard to available resources is close to the optimal performance obtained by exhaustive search and simulation. Therefore, the results clearly confirm that our algorithm is effective.

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Section: Experiments and Resultsmentioning

confidence: 99%

Run-time mapping algorithm for dynamic workloads using process merging transformations

Fatemi

Pimentel

2017

2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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“…We use estimated values of the computational latency, the area occupancy (on the FPGA), and the reconfiguration delay for each CCU. The computational latency values for the GPP model are initialized using the estimates obtained from literature [38,39] (non-Molen specific).…”

Section: Methodsmentioning

confidence: 99%

Evaluation of Runtime Task Mapping Using the rSesame Framework

Sigdel

Galuzzi

Bertels

et al. 2012

International Journal of Reconfigurable Computing

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Performing runtime evaluation together with design time exploration enables a system to be more efficient in terms of various design constraints, such as performance, chip area, and power consumption. rSesame is a generic modeling and simulation framework, which can explore and evaluate reconfigurable systems at both design time and runtime. In this paper, we use the rSesame framework to perform a thorough evaluation (at design time and at runtime) of various task mapping heuristics from the state of the art. An extended Motion-JPEG (MJPEG) application is mapped, using the different heuristics, on a reconfigurable architecture, where different Field Programmable Gate Array (FPGA) resources and various nonfunctional design parameters, such as the execution time, the number of reconfigurations, the area usage, reusability efficiency, and other parameters, are taken into consideration. The experimental results suggest that such an extensive evaluation can provide a useful insight both into the characteristics of the reconfigurable architecture and on the efficiency of the task mapping.

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“…), and various types of memory. The performance parameter values for these models are typically derived from datasheets or from measurements with lower-level simulators or real hardware platforms [43]. The structure of an architecture model -specifying which building blocks are used from the library and the way they are connected -is also described in YML within SESAME.…”

Section: Architecture Modelingmentioning

confidence: 99%

DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips

Stefanov

Pimentel

Nikolov

2017

Handbook of Hardware/Software Codesign

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The complexity of modern embedded systems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of system-level design. To cope with this design complexity, system-level design aims at raising the abstraction level of the design process from the register-transfer level (RTL) to the so-called electronic system level (ESL). However, this opens a large gap between deployed ESL models and RTL implementations of the MPSoC under design, known as the implementation gap. Therefore, in this chapter, we present the DAEDALUS methodology which the main objective is to bridge this implementation gap for the design of streaming embedded MPSoCs. DAEDALUS does so by providing an integrated and highly automated environment for application parallelization, system-level design space exploration, and system-level hardware/software synthesis and code generation.

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Calibration of Abstract Performance Models for System-Level Design Space Exploration

Cited by 50 publications

References 41 publications

Run-time mapping algorithm for dynamic workloads using process merging transformations

Run-time mapping algorithm for dynamic workloads using process merging transformations

Evaluation of Runtime Task Mapping Using the rSesame Framework

DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips

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