Ultralow-power SRAM technology

Abstract

An ultralow-standby-power technology has been developed in both 0.18-m and 0.13-m lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage sixtransistor (6T) SRAM cell sizes are 4.81 m 2 and 2.34 m 2 , corresponding respectively to the 0.18-m and 0.13-m design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25ЊC and is less than 400 fA per cell at 1.5 V, 85ЊC. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the wellknown gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

Analysis of the Effects of the Operating Temperature at the Performance and Leakage Power Consumption in a Conventional CMOS 6T-SRAM Bit-Cell at 65nm, 45nm, and 32nm Technologies

“…The gate tunneling leakage mechanism is active for the n-FET (T3) and p-FET (T6) sites shown in Fig 1. For the purpose described in this paper, the leakage is generally found to be adequately modeled for a given voltage as a function of gate-oxide thickness from the empirical relationship [5], for both the n-FETs and p-FETs.…”

“…However, it is worth pointing out that if the bitlines were held low (at ground), there would still be three devices in the cell contributing to the off-state leakage, since the internal nodes of the SRAM cell are held in opposite states. The off-state leakage can be adequately characterized given the subthreshold slope parameter (B1), an extracted parameter (A1) and threshold voltage (Vt) for both the n-FET and the p-FET with the following relationship [5].…”

“…This variation can be compounded in the SRAM cell by V th variations associated with overlay tolerances and corner-rounding effects due to aggressive scaling to achieve maximum density for the cell. Because of the exponential relationship of I off with V th , the contribution of the devices in the array with lower threshold voltage must be accounted for in calculating the overall array leakage [5,7].…”

“…The array leakage increase associated with the variation in the standard deviation of V th , i.e., (V th ), can be estimated by means of the following equation [5], Eq. (4) Where, is the V th mean, V td is the device V th , the subthreshold slope parameter (B 1 ), an extracted parameter (A 1 ).…”

An Innovative Design solution for minimizing Power Dissipation in SRAM Cell

“…Designer are more concerned about the power issues in the design rather than the speed and area of the design. Different design implementation present different power optimization opportunities [1].…”