Ultrahigh speed direct coupled logic gate fabricated with NbN/Pb Josephson junctions

Hatano, Yuji; Nishino, Tadashi; Tarutani, Y.; Kawabe, U.

doi:10.1063/1.94626

Cited by 11 publications

(1 citation statement)

References 11 publications

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“…OSEPHSON INTEGRATED CIRCUITS will be used in future computers due to high-speed and low-power dissipation [1]- [2]. Previously, a high-gain direct-coupled Josephson logic (HDCL) gate with a sub-10-ps switching delay was reported [3].…”

Section: Introductionmentioning

confidence: 99%

A 4.2-ps logic gate using new Pb-alloy Josephson IC technology

Nagata

Nakano

Mimura

et al. 1985

IEEE Electron Device Lett.

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A high-speed logic gate is attained using new Pb-alloy Josephson IC technology. Three design and fabrication techniques are developed for small I, scattering. They are a gate pattern design rule using junctions with identical geometrical construction, a double-layer resist stencil technique, and RF oxidation in COI plasma. A high-gain direct-coupled Josephson logic (HDCL) gate cascade chain is experimentally fabricated using a new 2-pm process developed from this technology. At a high current density of 10 kA/cm*, high quality junctions are obtained with a small Ij scattering of u = 6.8 percent. A very fast switching speed of 4.2 ps/gate is achieved.

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Section: Introductionmentioning

confidence: 99%

A 4.2-ps logic gate using new Pb-alloy Josephson IC technology

Nagata

Nakano

Mimura

et al. 1985

IEEE Electron Device Lett.

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Fabrication of NbN josephson junction integrated circuits using Si insulation layer

Hirano

Mori

Tarutani

et al. 1986

Electron Comm Jpn Pt II

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In the fabrication of Josephson junction integrated circuit, it is most important to align the superconducting critical current ImO of the junction. This paper reports a fabrication of interlayer insulating film with a view to reducing the fluctuation of ImO of NbN‐Oxide‐PbInAu junction of 1.5 μm. The main cause of the fluctuation of ImO is the variation of the junction area due to remnant of interlayer SiO insulating film generated in the aperture of the junction. To solve this problem, several interlayer insulators other than SiO have been investigated. It is found that Si is appropriate for forming the junction aperture without remnant. The Si film fabricated by evaporation has been a film close to amorphous. The pinhole defect density is 10/cm2 (film thickness 300 nm), which is smaller by two orders of magnitude than the one in SiO films. When Si films are used for interlayer insulation of NbN Josephson junction devices, the maximum distribution width of ImO is ±12% (σ ± 8%), which is about 1/2 for the case of SiO films. Usefulness of the film has been confirmed in application to the interlayer insulation film of the logic array with 750 gates. The measured delay time of a chain circuit made for trial is 14 ps/gate in a 2 input OR gate.

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Josephson Digital Devices

Hayakawa

Kotani

1993

Compound and Josephson High-Speed Devices

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Ultrahigh speed direct coupled logic gate fabricated with NbN/Pb Josephson junctions

Cited by 11 publications

References 11 publications

A 4.2-ps logic gate using new Pb-alloy Josephson IC technology

A 4.2-ps logic gate using new Pb-alloy Josephson IC technology

Fabrication of NbN josephson junction integrated circuits using Si insulation layer

Josephson Digital Devices

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