A 4.2-ps logic gate using new Pb-alloy Josephson IC technology

Fabrication technology for lead-alloy Josephson devices was evaluated from the viewpoint of application to large-scale integrated circuits. Metal and insulating layers used in the circuits were evaluated, and optimization of techniques for deposition or formation of these layers was investigated. Metallization of the Pb-In-Au base electrode and the Pb-Bi counterelectrode was studied in terms of optimizing the deposited films, to improve the reliability of junction electrodes. The formation of the oxide barrier was studied by in situ ellipsometry. SiOx deposited in oxygen was developed as the insulation layer with less defect density than conventional SiO. A liftoff technique using toluene soaking was developed, and patterns with a minimum line width of 2 μm were consistently reproduced. The characteristics of each element in the circuits were evaluated for test vehicles. For the junction, the following items were evaluated: controllability of the critical current Ic, junction quality, Ic uniformity, junction yield, and thermal cycling and storage stability. For the peripheral elements, integrity of lines and contacts, and characteristics of resistors were evaluated. 8-kbit memory cell arrays with a full vertical structure were fabricated to evaluate these technologies in combination. The continuity of each metal layer and insulation between metal layers were evaluated with an autoprober at room temperature. For selected chips, cell characteristics have been measured, and their Ic uniformity and production yields for cells are discussed. Normal operation of the memory cells was confirmed for all of the 24 accessible cells on a chip. Finally, we discuss the feasibility of Josephson large-scale integrated circuits using lead-alloy materials.

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Microstructure of fine-grained Pb-alloy films for Josephson integrated circuits

Hasumi

Waho

1986

Journal of Applied Physics

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The microstructure of Pb-In-Au alloy films is studied using transmission electron microscopy (TEM), Auger-electron spectroscopy (AES), and x-ray diffraction (XD) in order to obtain fine-grained films for high-reliability Josephson integrated circuits (ICs). TEM and XD observations are made to determine the film structure dependence on deposition technique. The techniques tested are molecular-beam condensation (MBC) and sequential deposition. Furthermore, AES analysis is performed to study the effect of the distribution of AuIn2 particles on the film structure. By using the MBC technique, fine-grained films are obtained with average grain sizes of 0.05–0.08 μm for about 0.2-μm-thick films. This result indicates that the MBC technique is promising for fabrication of high-reliability Pb-alloy Josephson ICs.

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A 4.2-ps logic gate using new Pb-alloy Josephson IC technology

Cited by 9 publications

References 2 publications

Hillock growth on PbInAu alloy films

Hillock growth on PbInAu alloy films

Fabrication technology for lead-alloy Josephson devices for high-density integrated circuits

Microstructure of fine-grained Pb-alloy films for Josephson integrated circuits

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