Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit

Trigate nanowire MOSFETs analog figures of merit

“…These values are much lower than the value expected from the V Th shift defined by variation of Fermi potential (DV Th /DT = D/ F /DT = 1.2-1 mV/°C for N A = 10 15 -10 16 cm À3 ). However, these values agree well with those previously reported for undoped FinFETs [14] and UTBB MOSFETs [11] as well as with simulations and theoretical predictions for undoped ultra-thin FD SOI devices [11,15]. SS variation with temperature follows the ideal kT/q Á ln(10) dependence and does not exceed 40 mV/dec over the 25-225°C temperature range.…”

“…SS variation with temperature follows the ideal kT/q Á ln(10) dependence and does not exceed 40 mV/dec over the 25-225°C temperature range. These values are in line with those previously achieved in undoped FinFETs [14] and UTBB MOSFETs [11]. The main reasons of the ideal SS temperature behavior are almost-zero degradation of gateto-channel coupling and a very limited deviation from the exponential dependence of the inversion charge density on the surface potential with temperature increase in the case of thin Si films (particularly with multi-gate control).…”

“…Fig. 9 benchmarks the g m -A v0 analog metric of TGNW devices with those previously reported for other advanced devices, such as UTBB MOSFETs [11] and FinFETs [12]. It is well known that strain introduction in the channel leads to performance improvement, particularly in terms of g m and I d .…”

“…It is worth noting that, contrarily to ultra-thin body with ultrathin BOX (UTBB) MOSFETs [11], analog FoM of TGNW MOSFETs in the first order are expected to be free from the effect of the applied substrate bias. This is due to (i) the thick BOX in TGNWs (145 nm compared with 10 or 25 nm in UTBB) and (ii) the trigate control of the channel which screens the substrate effect in narrow devices.…”

“…The main reasons of the ideal SS temperature behavior are almost-zero degradation of gateto-channel coupling and a very limited deviation from the exponential dependence of the inversion charge density on the surface potential with temperature increase in the case of thin Si films (particularly with multi-gate control). More details on theory of V Th and SS temperature behavior can be found in [11,[14][15][16]. Due to the well-controlled V Th and SS variation with temperature and the small active volume, I off and I on /I off degradations with temperature are limited and excellent values of I off < 50 nA/lm and I on /I off > 2 Â 10 4 (at 225°C and V d = 1 V) can be achieved.…”