Trigate nanowire MOSFETs analog figures of merit

Kilchytska, Valeriya; Makovejev, Sergej; Barraud, S.; Poiroux, T.; Raskin, Jean‐Pierre; Flandre, Denis

doi:10.1016/j.sse.2015.02.003

Cited by 15 publications

(8 citation statements)

References 13 publications

(29 reference statements)

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“…Figure 3b demonstrates effect of temperature on gm-Av metric revealing strong device performance improvement with temperature reduction. gm values are strongly improved thanks to mobility enhancement at cryogenic temperatures, particularly in a "long"-channel devices; slight improvement of Av is also observed (more details can be found in [56]). Effect of the back-gate bias in UTBB FDSOI is shown in Fig.…”

Section: B Gm -Av Analog Metricmentioning

confidence: 96%

“…Figure 3 gives a couple of concrete examples of gm-Av technique application on advanced MOSFETs. Figure 3a shows effect of NW width with a clear improvement of the device performance both in terms of gm and Av in "narrow" NWs comparing to their wide counterpart [56]. This is because of improved control of the SCE and "volume inversion" (i.e.…”

Section: B Gm -Av Analog Metricmentioning

confidence: 99%

“…Indeed, negative Vbg pushes the channel towards the top Si interface with high-k gate oxide, whereas positive one attracts it towards the bottom Si interface with a SiO2 BOX, which is less defective than high-k interface so that higher mobility is obtained [36,46]. Figure 2b gives the example of NWs, plotting Id/(W/L) extracted at gm/Id of 10 and 5 V -1 as a function of NW width [56]. One can see that while normalized Id is almost constant for "long" NW MOSFET, strong improvement is observed with NW width reduction in the case of "short" device.…”

Section: Dc-based Techniques (Or Techniques Based On Static Measmentioning

confidence: 99%

“…Therefore, the usually observed [39,83,92] Id (and gm) improvement with increase of NW (or Fin) width, related to the mobility improvement when conduction is dominated by the top-plane w.r.t sidewalls, almost does not appear in these devices featuring a complex 3D conduction. More details can be found in [56]. shows effect of "strain" introduced into the channel of SOI-based FinFETs on gm/Id versus Id/(W/L) curve [58].…”

Section: Dc-based Techniques (Or Techniques Based On Static Measmentioning

confidence: 99%

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Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

Kilchytska

Makovejev²,

Esfeh

et al. 2021

IEEE J. Electron Devices Soc.

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This review paper assesses the main approaches in the electrical characterization of advanced MOSFETs towards their future analog and RF applications. Those approaches are shown to be different from the traditionally used ones for the assessment of the device perspectives for digital applications. Based on the original research realized by our group over the last years, advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as Fully Depleted Silicon-on-Insulator (FDSOI), FinFETs and NanoWires (NW) in a wide temperature range (from cryogenic, 4 K up to 250°C). A wide frequency band characterization (from DC up to hundred GHz range) will be positioned as a key element enabling a fair device assessment towards analog and RF applications. Importance of the "extrinsic" parasitic elements in the advanced devices is enormous, sometimes even dominating the device performance. Therefrom arises the need for a proper separate extraction and discussion of "intrinsic" versus "extrinsic" parameters.

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Section: B Gm -Av Analog Metricmentioning

confidence: 96%

Section: B Gm -Av Analog Metricmentioning

confidence: 99%

Section: Dc-based Techniques (Or Techniques Based On Static Measmentioning

confidence: 99%

Section: Dc-based Techniques (Or Techniques Based On Static Measmentioning

confidence: 99%

See 2 more Smart Citations

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

Kilchytska

Makovejev²,

Esfeh

et al. 2021

IEEE J. Electron Devices Soc.

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“…Embora existam diversos estudos sobre nanofios transistores MOS na literatura, estes exploram, majoritariamente, o funcionamento dos dispositivos com foco para aplicações digitais (COQUAND et al, 2012b;DESHPANDE et al, 2012;LAI et al, 2011;SAITOH et al, 2010). Poucos trabalhos tratam da operação de NWs em regime de saturação com foco para parâmetros analógicos (KILCHYTSKA et al, 2015). Assim, ainda existem muitos assuntos a serem explorados quanto aos parâmetros analógicos de NWs, como a influência da baixa temperatura e o uso de tensionamento mecânico.…”

Section: Introductionunclassified

Avaliação da influência da evolução das tecnologias de fabricação de nanofios transistores MOS sobre suas características elétricas

Paz¹

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This work aims to study the influence of different fabrication technologies of inversion mode nanowires MOS transistors (NWs) through the evaluation and comparison of their electrical characteristics obtained from experimental measurements. Tridimensional numerical simulations are also used to allow the understanding of observed physical effects and to validate parameters extraction methods proposed in this work. Following the technological evolution of fabrication of NWs recently proposed, the influence of fin width, strain and stacking of nanowires is verified, mainly, over analog behavior and carriers' mobility. The comparisons performed in this work allow picking the technology that presents the best performance for each parameter analyzed. Several nanowires with fin width as narrow as 9.5nm and up to 10µm (quasi-planar) are analyzed. The fin width influence on the analog parameters is studied for n-and p-type non-stacked NWs with channel lengths of 10µm and 40nm. Effective mobility results are correlated to the harmonic distortion to explain linearity peaks behavior with temperature and fin width. Narrow transistors show improved linearity mainly due to higher intrinsic voltage gain. Back bias influence is studied in narrow NWs, where mobility varies due to carriers' density and inversion channel position along the fin. Strained and unstrained n-type NWs are compared using experimental results in the temperature range of 300 down to 10K, where mobility behavior is the major responsible for the analog parameters dependence on temperature. Uniaxial compressive strain obtained through SiGe in p-type nanowires shows to be beneficial for mobility, where improvements reach up to 68% for fin width of 20nm at room temperature. Strained vertically stacked p-type SOI nanowires with inner spacers and [110]-and [100]-oriented channels are studied as a function of both fin width and channel length. Procedures to extract the effective oxide thickness and fin width are adapted and validated through tridimensional numerical simulations. Overall effective mobility for stacked NWs is lower in comparison to nonstacked NWs due to small contribution from the top GAA level and threshold voltage mismatches, according to the investigation promoted by the proposed methodology to dissociate the low field mobility contributions from the top and bottom levels that compose the stacked structure.

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