“…For such applications, antimonide-based compound semiconductor (ABCS) InAs/AlSb HEMTs are particularly promising because of their combination of high electron mobility and peak velocity, along with high electron concentration in the 2DEG that results in unparalleled speed-power performance. The InAs/AlSb HEMT's inherent low-voltage operation, with below 0.5 V, can reduce dc power dissipation by an order of magnitude compared with a GaAs PHEMT of equivalent performance [1], [2], and by a factor of three to four compared to an equivalent InP HEMT [3], [4]. In the case of active-array space-based radar applications, ABCS LP-LNAs are a system enabler because they permit a substantial reduction in the required spacecraft prime power and corresponding spacecraft weight and launch cost [5], [6].…”
“…For such applications, antimonide-based compound semiconductor (ABCS) InAs/AlSb HEMTs are particularly promising because of their combination of high electron mobility and peak velocity, along with high electron concentration in the 2DEG that results in unparalleled speed-power performance. The InAs/AlSb HEMT's inherent low-voltage operation, with below 0.5 V, can reduce dc power dissipation by an order of magnitude compared with a GaAs PHEMT of equivalent performance [1], [2], and by a factor of three to four compared to an equivalent InP HEMT [3], [4]. In the case of active-array space-based radar applications, ABCS LP-LNAs are a system enabler because they permit a substantial reduction in the required spacecraft prime power and corresponding spacecraft weight and launch cost [5], [6].…”
“…where is an integer that ( + More generally, if there are phases to be selected, the output frequency would be = ( + ) , (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20)(21) and the tuning step would be ∆ = . (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20)(21)(22) This means that a finer tuning step can be achieved with more phases provided. The average shifted phase number during each is thus…”
Section: Constant-step Phase Switchingmentioning
confidence: 99%
“…It was the time when designers faced many challenges when fabricating RF circuits on CMOS process. However, many of these challenges have been resolved, such as high-quality on-chip inductors [1]- [4], wide-band CMOS oscillators [5]- [7], CMOS low-noise amplifiers [8]- [10], etc. Moreover, due to the surge of consumer electronics such 2 as smartphones and entertainment electronics, wireless applications evolve towards low power, small dimensions, higher yield, and higher level of integration owing to its low cost.…”
mentioning
confidence: 99%
“…As will be seen later, this is much lower than the contribution from phase noise of the oscillator. However, (4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15) does limit the signal bandwidth as the quantization noise increases dramatically with .…”
Phase-locked loops (PLLs) have been successfully used as frequency synthesizers for decades in complementary metal-oxide-semiconductor (CMOS) transceivers for wireless communications. However, modern developments in communications require PLLs with wider loop bandwidth and lower in-band phase noise. High in-band phase noise leads to serious consequences in communications, such as degraded signal-to-noise ratio (SNR) and constellation diagram, resulting in low communication quality. Therefore, low PLL in-band phase noise is crucial to the overall transceiver performance, especially in future high-speed high-quality wireless communications. Unfortunately, frequency synthesizers based on conventional PLL structures are facing challenges because their in-band phase noise is often limited by the phase detectors and charge pumps. Noises from these components are amplified due to the structure of the conventional PLLs. Furthermore, PLL often needs to achieve short settling time for some communication standards, and has to provide multi-phase output in some transceiver architectures. Inspired by these requirements, this thesis aims to enhance PLL in-band phase noise performance while meeting other important requirements of future wireless communications in the multi-GHz band.
“…These systems demand for low noise amplifiers (LNAs) with low DC power consumption. There have been a number of recent papers on low power LlVAs in the range of 900 MHdL-band [1,2] and S-band [3,4,5]. Generally the lowest noise figures are obtained with heterojunction FETs (HEMTs) or bipolar transistors (HBTs).…”
A two stage monolithic integrated low noise amplifier for applications in the wireless data frequency range of 5 to 6 GHz has been designed. A noise figure of 3.5 dB with a gain of 15 dB has been achieved using enhancement MESFETs only. The LNA draws 3 mA from a 3.3 V supply, achieving a gain/PDc figure of merit of 1.5 dB/mW.
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