Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET

Ni, Chi-Nung; Li, X.; Sharma, Shashank; Rao, K. V.; Jin, Miao; Lazik, C.; Banthia, V.; Colombeau, B.; Variam, N.; Mayur, A. J.; Chung, Hua; Hung, R.; Brand, A.

doi:10.1109/vlsit.2015.7223711

Cited by 29 publications

(18 citation statements)

References 2 publications

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“…Therefore, we perform a systematic thermal stability study of a typical MIS contact: Ti/TiO 2 /n-Si. TiO 2 is one of the most frequently investigated candidates for MIS application because of its relatively low conduction band offset with n-Si and n-Ge [12]- [14]; Ti is a typical low-WF metal (WF of ∼4.3 eV), which is presently the prevailing source/drain contact metal in modern CMOS [10], [15].…”

Section: Introductionmentioning

confidence: 99%

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO₂/n-Si Contact

Schaekers

Schram

et al. 2016

IEEE Trans. Electron Devices

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This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height (qϕ b ) MIS contact: Ti/TiO 2 /n-Si. By incorporating different levels of donor concentration in n-Si, we perform a systematic Ti/TiO 2 /n-Si thermal stability study under different electron conduction mechanisms. We find that both qϕ b and contact resistivity (ρ c ) of the Ti/TiO 2 /n-Si MIS contacts vary dramatically after mere 300°C-500°C 1-min rapid thermal treatments. The variations in qϕ b and ρ c are related to the thermally driven TiO 2 decomposition. This thermal stability study of Ti/TiO 2 /n-Si reveals a general concern for the MIS contact application: since the MIS contacts on n-type semiconductor generally utilize a reactive low-work function metal and an ultrathin insulator, it is difficult to maintain their interface quality considering the thermal budget in standard manufacturing of integrated circuits. Possible solutions to this MIS thermal stability issue are discussed.

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Section: Introductionmentioning

confidence: 99%

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO₂/n-Si Contact

Schaekers

Schram

et al. 2016

IEEE Trans. Electron Devices

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“…However, despite the low q<pbn advantage, the pe benchmark on n-Si in Fig. 4 [4] , [14], [21], [28], [29], [35] reveals that the lowest reported pe of MIS on n-Si are still high (~1 x 10-s Q ' cm 2 [14], [28]) and are 4-5 times higher than the lowest reported pe ofMS counterpart [11], [29]. Ti/Ti02/n-Si contact with low q<j>bn of ~O.l eV shows perfect ohmic behavior on Schottky barrier diodes (SBD) while Ti/n-Si with q<j>bn of ~0.5 eV shows typical rectifying behavior; however, Ti/0.8nm Ti02/n+-Si shows more than one order of magnitude higher pe than Ti/n+-Si.…”

Section: Mis or Ms For N-type Semiconductor?mentioning

confidence: 99%

“…For instance, although NiSix [4], [43] or NiGex [23], [25] with ultralow pe have been demonstrated, the fast diffusion ofNi in Si or Ge creates precipitate defects and induces concerns of device reliability [44], [45]. Therefore, Ni has been gradually superseded in modern CMOS, Currently Ti becomes the prevailing contact metal in modern CMOS [1], [11], [29]. As shown in Fig.…”

Section: B Thermal Stability Problem Of Mls On N-type Semiconductormentioning

confidence: 99%

“…MR-CTLM was recently developed for ultralow pe study [6]. It has the simplest process and probably also the highest precision among the few modern test structures that are able to accurately determine pe below lx1O· 8 Q'cm 2 [7]- [11]. The small metal electrode, contact chain design, and simple process contribute together to the outstanding accuracy and repeatability ofMR-CTLM.…”

Section: Introductionmentioning

confidence: 99%

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MIS or MS? Source/drain contact scheme evaluation for 7nm Si CMOS technology and beyond

Schaekers

Demuynck

et al. 2016

2016 16th International Workshop on Junction Technology (IWJT)

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Contact resistance at the transistor source/drain becomes a bottleneck for modern Si CMOS technology. To seek for contact solutions, this paper compares metal-insulator-semiconductor (MIS) contacts and metal-semiconductor (MS) direct contacts in terms of contact resistivity and CMOS compatibility. On p-type substrates, due to the favorable surface Fermi level pinning, MS contact has absolute advantage over MIS. On n-type substrates, on the one hand, we find MIS contacts have relatively high contact resistivity despite the low Schottky barrier height; the low thermal stability of MIS is also worrying. On the other hand, with MS contacts, we use a pre-amorphization based Ti silicidation technique and achieve contact resistivity of 1.5xl0-9 n·cm 2 • Therefore, for both NMOS and PMOS, we confirm that MS contacts are still the prevailing contact scheme. Advanced MS interface engineering is able to help reach the target contact resistivity required by advanced CMOS technology.

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“…The generation of free carriers requires achieving high concentration of electrically active dopants, typically controlled by doping and annealing techniques. The selective growth of in-situ doped epitaxial Si:P [1][2][3][4] is a major innovation that can significantly reduce source-drain external resistance and simultaneously act as stressor for advanced field effect transistor options beyond 3nm including gate-all-around (GAA) nanowire and FinFET devices. [5][6][7] The continuing device scaling demands for ever-increasing phosphorus concentration [P] in epitaxial Si:P. There has been significant efforts to increase phosphorus concentration [P] in epitaxial Si:P, and the highest [P] achieved nowadays is about 3x10 21 at./cm 3 by state-of-the-art epitaxial Si:P processes, virtually limited by its solid solubility.…”

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confidence: 99%

Achieving junction stability in heavily doped epitaxial Si:P

Tsai

Hsu

Santos

et al. 2021

Materials Science in Semiconductor Processing

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Junction stability and donor deactivation in silicon at high doping limit has been a longstanding issue in advanced semiconductor devices. Recently, heavily doped epitaxial Si:P layer with phosphorus concentrations as high as 3 x 10 21 at. /cm 3 has been employed in nanowire field-effect transistor (FET) devices for sub-3 nm technology node as low resistance sourcedrain and channel stressor. In such highly doped Si:P, the actual dopant activation is much less than nominal phosphorus concentration due to inactive phosphorus atoms arising from dopantvacancy defects (PnV) clustering phenomenon. Even with state-of-the-art high temperature millisecond annealing, this epitaxial film is thermally unstable upon subsequent thermal treatments. To overcome this limitation, we demonstrate a selective dopant activation scheme

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Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET

Cited by 29 publications

References 2 publications

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO₂/n-Si Contact

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO₂/n-Si Contact

MIS or MS? Source/drain contact scheme evaluation for 7nm Si CMOS technology and beyond

Achieving junction stability in heavily doped epitaxial Si:P

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Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET

Cited by 29 publications

References 2 publications

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO2/n-Si Contact

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO2/n-Si Contact

MIS or MS? Source/drain contact scheme evaluation for 7nm Si CMOS technology and beyond

Achieving junction stability in heavily doped epitaxial Si:P

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Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO₂/n-Si Contact

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO₂/n-Si Contact